cvw/fpga/generator/Makefile

dst := IP


all: $(dst)/xlnx_proc_sys_reset.log \
	$(dst)/xlnx_ddr4.log \
	$(dst)/xlnx_axi_clock_converter.log \
	 $(dst)/xlnx_ahblite_axi_bridge.log

$(dst)/%.log: %.tcl
	mkdir -p IP
	cd IP;\
	vivado -mode batch -source ../$*.tcl | tee $*.log

clean:
	rm -rf IP vivado.jou vivado.log
Created Makefile to manage IP generation. 2021-11-30 00:32:51 +00:00			`dst := IP`


			`all: $(dst)/xlnx_proc_sys_reset.log \`
			`$(dst)/xlnx_ddr4.log \`
			`$(dst)/xlnx_axi_clock_converter.log \`
			`$(dst)/xlnx_ahblite_axi_bridge.log`

			`$(dst)/%.log: %.tcl`
			`mkdir -p IP`
			`cd IP;\`
			`vivado -mode batch -source ../$.tcl \| tee $.log`
Added make clean to fpga IP generator. 2021-11-30 00:42:28 +00:00
			`clean:`
			`rm -rf IP vivado.jou vivado.log`