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Configurable RISC-V Processor
1,581 Commits 14 Branches 1 Tag 31 MiB
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C 27.2%
SystemVerilog 8.2%
Python 2.7%
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fc7016eea6
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Ross Thompson fc7016eea6 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 
Fixed logic for trace update in the M and W stages.  The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
riscv-coremark Updated location to find compiler for coremark 2021-07-16 19:13:18 -04:00
testsBP
wally-pipelined Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 2021-08-08 00:28:18 -05:00
.gitattributes
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor