Ross Thompson 61f7bad739 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2022-10-18 15:06:09 -05:00
..
cache	Reordered the eviction and fetch in cache so it follows a more logical order.	2022-10-04 17:36:07 -05:00
ebu	Merged cacheable with seluncachedadr.	2022-10-17 13:29:21 -05:00
fpu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-10-13 22:36:57 +00:00
generic	changed always_ff to always in sram1p1rw to fix testbench complaint	2022-09-25 19:56:40 -07:00
hazard	Possible fix for interrupt during a floating point divide.	2022-10-18 15:04:21 -05:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	Merged cacheable with seluncachedadr.	2022-10-17 13:29:21 -05:00
lsu	Merged cacheable with seluncachedadr.	2022-10-17 13:29:21 -05:00
mmu	Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.	2022-10-05 14:51:02 -05:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.	2022-10-02 16:21:21 -05:00
uncore	Updated uart settings and fpga wave config.	2022-10-18 15:05:33 -05:00
wally	Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing	2022-10-10 07:12:37 -07:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00