bbracker a683dd7fde Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2021-06-02 10:03:23 -04:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Edited and added constants to support SV48	2021-06-01 17:49:45 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00
src	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-02 10:03:23 -04:00
testbench	Updates to muldiv.sv for 32-bit div/rem	2021-06-01 15:31:07 -04:00
testgen	Forgot to add csr permission tests to testbench	2021-05-04 20:20:22 -04:00
lint-wally	slightly more path independence for using verilator	2021-05-24 18:11:56 -04:00