Ross Thompson 3f780f012a Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. ... Also forgot to include cacheLRU.sv file.		2021-07-20 23:17:42 -05:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Partially working 2 way set associative d cache.	2021-07-20 17:51:42 -05:00
linux-testgen	change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)	2021-07-19 19:30:29 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Partially working 2 way set associative d cache.	2021-07-20 17:51:42 -05:00
src	Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux.	2021-07-20 23:17:42 -05:00
testbench	ignore mhpmcounters because QEMU doesn't implement them	2021-07-20 13:37:52 -04:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00