Ross Thompson 16e037b8e9 Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.		2021-05-24 23:24:54 -05:00
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bpred.sv	Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.	2021-05-24 23:24:54 -05:00
BTBPredictor.sv	Corrected a number of bugs in the branch predictor.	2021-03-31 11:54:02 -05:00
decompress.sv	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
globalHistoryPredictor.sv	fixed bug in gshare, global and local history BP	2021-04-29 06:14:32 -04:00
gshare.sv	fixed bug in gshare, global and local history BP	2021-04-29 06:14:32 -04:00
icache.sv	Fixed minor bug in instruction class decoding.	2021-05-24 13:41:14 -05:00
icacheMem.sv	Fixed synthesis bug with icache valid bit.	2021-05-04 13:03:08 -05:00
ifu.sv	Fixed minor bug in instruction class decoding.	2021-05-24 13:41:14 -05:00
localHistoryPredictor.sv	Fixed typo in ifu for bypassing branch predictor.	2021-05-03 08:56:45 -05:00
RAsPredictor.sv	Corrected a number of bugs in the branch predictor.	2021-03-31 11:54:02 -05:00
satCounter2.sv	We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.	2021-02-15 14:51:39 -06:00
SramModel.sv	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.	2021-02-18 21:32:15 -06:00
twoBitPredictor.sv	Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.	2021-05-24 23:24:54 -05:00