Configurable RISC-V Processor
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Ross Thompson 2cca457f14 Imperas found a bug with the Fence.I instruction.
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 09:41:18 -06:00
addins sram1p1rw cleanup 2022-12-20 02:57:51 -08:00
benchmarks added additional cache stats to coremark postprocess script 2022-10-25 02:56:25 +00:00
bin Updated branch predictor. 2023-01-11 17:00:45 -06:00
examples Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest 2022-09-21 10:35:08 -07:00
fpga Updated constraints to remove DivBusyE. 2022-12-30 10:51:35 -06:00
linux Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
pipelined Imperas found a bug with the Fence.I instruction. 2023-01-20 09:41:18 -06:00
synthDC Rolled back synth scripts to fff91ae commit before Madeleine's modifications to write config files; the modified version is failing right away with trouble copying configs 2022-08-24 00:09:16 +00:00
tests Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
.gitattributes Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
.gitignore update 2023-01-19 13:29:46 +00:00
.gitmodules fixed gitmodules 2022-07-21 10:15:13 -07:00
bugs.txt Fixed bug. 2022-02-11 14:00:01 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
Makefile Updated Makefile to reflect new Linux and Imperas situation. Updated setup to include Synopsys license file. 2022-03-03 11:28:22 -08:00
README.md Update README.md 2022-01-24 15:47:42 -08:00
setup.imperas.sh Merge branch 'imperas' of github.com:davidharrishmc/riscv-wally into imperas 2023-01-20 08:38:08 -06:00
setup.sh added finish message to setup 2022-12-23 22:53:39 -08:00

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

If you are new to using Linux and Github, follow the steps in the RISCV SoC Design textbook to:

See Chapter 2 of draft book of how to install and compile tests.

Download and install x2go - A.1
Download and install VSCode - A.4.2
Make sure you can log into Tera acceptly via x2go and via a terminal
	Terminal on Mac, cmd on Windows, xterm on Linux
	See A.1 about ssh -Y login from a terminal
Git started with Git configuration and authentication: B.1

Then follow Section 2.2.2 to clone the repo, source setup, make the tests and run regression

$ cd
$ export RISCV=/opt/riscv
$ git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally
$ cd riscv-wally
$ source ./setup.sh
$ make
$ cd pipelined/regression
$ ./regression-wally       (depends on having Questa installed)

Add the following lines to your .bashrc or .bash_profile

if [ -f ~/riscv-wally/setup.sh ]; then
	source ~/riscv-wally/setup.sh
fi