Ross Thompson
2cca457f14
Imperas found a bug with the Fence.I instruction.
...
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is
to ensure the cache continues to assert Stall while in WriteLine state.
There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 09:41:18 -06:00
Ross Thompson
ce7d92f2dc
Merge branch 'imperas' of github.com:davidharrishmc/riscv-wally into imperas
2023-01-20 08:38:08 -06:00
Lee Moore
5de1801100
Merge pull request #13 from eroom1966/imperas
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Merge pull request #5 from davidharrishmc/imperas
2023-01-20 14:34:38 +00:00
Lee Moore
bc0497687c
Merge pull request #5 from davidharrishmc/imperas
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Merge pull request #12 from eroom1966/imperas
2023-01-20 14:33:21 +00:00
Lee Moore
97619eee87
Merge pull request #12 from eroom1966/imperas
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Imperas
2023-01-20 14:32:57 +00:00
Lee Moore
9dd771933b
Merge pull request #4 from davidharrishmc/imperas
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Merge pull request #11 from eroom1966/imperas
2023-01-20 14:32:21 +00:00
eroom1966
9fe515c78e
Merge branch 'imperas' of https://github.com/eroom1966/riscv-wally into imperas
2023-01-20 14:31:17 +00:00
Lee Moore
74610d0aa8
Merge pull request #11 from eroom1966/imperas
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Imperas
2023-01-19 14:56:44 +00:00
Lee Moore
81d6517732
Merge branch 'davidharrishmc:imperas' into imperas
2023-01-19 14:56:18 +00:00
eroom1966
d9d5b99218
update
2023-01-19 13:29:46 +00:00
eroom1966
a34a1e6238
correct the HASH
2023-01-19 10:41:11 +00:00
Lee Moore
165975d853
Merge pull request #10 from eroom1966/imperas
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Imperas
2023-01-19 10:28:27 +00:00
Lee Moore
ec84ce98ab
Merge pull request #3 from davidharrishmc/imperas
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Imperas
2023-01-19 10:27:52 +00:00
eroom1966
b53cb9eb20
customer commands
2023-01-19 10:20:55 +00:00
Ross Thompson
3fc11f506f
Merge branch 'imperas' of github.com:davidharrishmc/riscv-wally into imperas
2023-01-18 16:04:02 -06:00
Ross Thompson
e900914d3a
Modified to clone imperas via git rather than https.
2023-01-18 15:49:42 -06:00
Lee Moore
ac935b1040
Merge pull request #9 from eroom1966/imperas
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Partial fix for misaligned LD/ST
2023-01-18 17:12:19 +00:00
eroom1966
7c0cad148d
Partial fix for misaligned LD/ST
2023-01-18 17:11:39 +00:00
Lee Moore
3f04892cde
Merge pull request #8 from eroom1966/imperas
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changes made with Ross
2023-01-18 16:48:22 +00:00
eroom1966
2e4e5f9c61
changes made with Ross
2023-01-18 16:46:48 +00:00
ross144
1d868eb31e
Merge pull request #7 from eroom1966/imperas
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Imperas
2023-01-18 09:27:39 -06:00
eroom1966
a5a5b7a408
add im flags for compressed disass
2023-01-18 13:37:28 +00:00
eroom1966
df4419dea2
remove volatile for FFLAGS and FCSR
2023-01-18 13:33:57 +00:00
eroom1966
c18942bd0b
refer to correct path
2023-01-18 13:26:07 +00:00
eroom1966
eb67abdcda
ignore external
2023-01-18 13:22:32 +00:00
eroom1966
538940e269
update for private copy of Imperas
2023-01-18 13:19:14 +00:00
Lee Moore
ab996cb370
Merge pull request #2 from davidharrishmc/imperas
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Imperas
2023-01-18 09:14:07 +00:00
Ross Thompson
b30c13a188
Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage.
2023-01-17 18:24:46 -06:00
ross144
9b62047f4b
Merge pull request #2 from eroom1966/imperas
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Imperas
2023-01-17 14:50:05 -06:00
eroom1966
8caa93ce4d
refactor all rvvi into single initial block
2023-01-17 13:01:01 +00:00
eroom1966
f4e7e54abe
Code refactor and addition of rvvi interface
2023-01-17 12:47:38 +00:00
Lee Moore
aea9cc1a75
Merge pull request #1 from davidharrishmc/imperas
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Imperas
2023-01-17 09:23:41 +00:00
Ross Thompson
7c4eaa1ca6
Found a potential issue with mstatush when XLEN = 64.
2023-01-16 13:57:28 -06:00
Ross Thompson
fabe13bdce
Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs.
2023-01-16 13:35:06 -06:00
Ross Thompson
4aa2b5737f
Signal renames for ras.
2023-01-13 15:56:10 -06:00
Ross Thompson
0e215ac3c6
Removed 1 bit from instruction classification.
2023-01-13 15:19:53 -06:00
Ross Thompson
de7f3b14fc
More branch predictor cleanup.
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Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
2023-01-13 12:57:18 -06:00
Ross Thompson
cf608ee45f
Possible optimization of gshare.
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I don't believe the Writeback stage ghr is needed.
2023-01-13 12:39:29 -06:00
Ross Thompson
ea7c447218
Possible minor enhancement to gshare.
2023-01-13 12:32:39 -06:00
Ross Thompson
395b7a5b32
Nearly complete RVVI tracer.
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Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
2023-01-12 18:43:39 -06:00
Ross Thompson
ef4c684336
Added supervisor mode registers to tracer.
2023-01-12 17:04:41 -06:00
Ross Thompson
9917be817c
Added M CSRs to the CSRArray.
2023-01-12 16:51:51 -06:00
Ross Thompson
a68773eba1
added machine csr to logger.
2023-01-12 16:35:19 -06:00
Ross Thompson
2e622c9860
Added support to print the gprs.
2023-01-12 16:09:30 -06:00
Ross Thompson
4733b787f8
rvvi trace is coming alone nicely.
2023-01-12 14:46:31 -06:00
Ross Thompson
3cc37e3f12
Completely stripped down imperas simulation.
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run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
2023-01-12 12:48:38 -06:00
Ross Thompson
2f2f3d6da5
Stripped out all signature checking.
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Removed multiple tests loop.
Only runs 1 test now.
2023-01-12 12:45:44 -06:00
Ross Thompson
5ad0bacf5b
Created separate imperas testbench.
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Resolved logger issue with the duplicated instructions after commit.
2023-01-12 12:07:07 -06:00
Ross Thompson
94f24d3f58
Added instruction logger.
2023-01-12 10:09:34 -06:00
Ross Thompson
e0867b1840
Completed review of LSU.
2023-01-11 19:06:03 -06:00
