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  • 05d362e334 regression: use busybear batch instead Noah Boorstin 2021-03-25 15:34:10 -0400
  • 56a32b5882 More bug fixes for privileged tests Domenico Ottolia 2021-03-25 15:05:55 -0400
  • 3b4f0141f4 Begin work on compressed instructions Jarred Allen 2021-03-25 14:43:10 -0400
  • 44060b579b busybear: quick fix to mem reading Noah Boorstin 2021-03-25 14:29:10 -0400
  • 162f2df880 FPU Pipeline completed - can begin integration Brett Mathis 2021-03-25 13:29:03 -0500
  • f134b09a97 Fix bugs with privileged tests Domenico Ottolia 2021-03-25 14:06:05 -0400
  • d02c88dab5 busybear: stop NOPing out atomics Noah Boorstin 2021-03-25 13:29:16 -0400
  • ee36f4e09b Added WALLY-PIPELINE test to rv64wally David Harris 2021-03-25 13:18:50 -0400
  • 0290568a52 Make cache output NOP after a reset Jarred Allen 2021-03-25 13:18:30 -0400
  • eb9787609e testgen-PIPELINE python startup David Harris 2021-03-25 13:12:18 -0400
  • 21989ee615 adding PIPELINE tests Shriya Nadgauda 2021-03-25 13:07:25 -0400
  • ce6f102fc5 Clean up some stuff Jarred Allen 2021-03-25 00:46:51 -0400
  • 128278ea27 Working for all of rv64i now, but not compressed instructions Jarred Allen 2021-03-24 17:23:00 -0400
  • 602271ff7b rv64i linear control flow now working Jarred Allen 2021-03-24 16:56:44 -0400
  • ba95557c44 More progress on icache controller Jarred Allen 2021-03-24 13:58:43 -0400
  • ad0d77e9e1 Begin rewrite of icache module to use a direct-mapped scheme Jarred Allen 2021-03-24 13:40:08 -0400
  • ebd6b931c6 Fix bug in cache line Jarred Allen 2021-03-24 13:39:45 -0400
  • b774d35c34 Output NOP instead of BAD when reset Jarred Allen 2021-03-25 12:42:48 -0400
  • 4b92a595ab Merge branch 'main' into cache Jarred Allen 2021-03-25 12:10:26 -0400
  • 51291949d8 Config file for ppa experiments Teo Ene 2021-03-25 10:23:21 -0500
  • a8abd47fbc Added PPA README David Harris 2021-03-25 11:21:31 -0400
  • e3900bd0fa Finish finite state machines for page table walker Thomas Fleming 2021-03-25 02:48:40 -0400
  • 7367052e76 Add vscode and pycache folders to .gitignore Thomas Fleming 2021-03-25 02:37:50 -0400
  • b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-03-25 02:35:21 -0400
  • a3788eb218 added 1 tick delay to dtim flops bbracker 2021-03-25 02:23:30 -0400
  • b5fa410e15 added 1 tick delay on tim reads bbracker 2021-03-25 02:15:28 -0400
  • 682050a33b Merge branch 'main' into cache Jarred Allen 2021-03-25 00:51:12 -0400
  • 67b27cd2f5 instrfault direspecting stalls bugfix bbracker 2021-03-25 00:44:35 -0400
  • 02e924e55a instrfaults not respecting stalls bugfix bbracker 2021-03-25 00:16:26 -0400
  • 1e3f683a9d upgraded gpio bus interface bbracker 2021-03-25 00:15:02 -0400
  • 717257d9ac gitignore FunctionRadix.addr bbracker 2021-03-25 00:13:46 -0400
  • e98dd420bc future work comment about suspicious-looking verilog in csri.sv bbracker 2021-03-25 00:10:44 -0400
  • b1d849c822 Add all PMP addr registers Thomas Fleming 2021-03-24 21:58:33 -0400
  • f5b70c8ab8 Manual assembly hack to prevent RV64IM coremark from EBREAKing early Teo Ene 2021-03-24 18:05:34 -0500
  • a3aa103dc7 Fix typo from last commit Teo Ene 2021-03-24 17:09:58 -0500
  • 4427b5ec01 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Teo Ene 2021-03-24 17:04:48 -0500
  • e43849b82c Updated coremark_bare testbench for IM Teo Ene 2021-03-24 17:04:43 -0500
  • 18cb1f4873 fixed various bugs in the FMA Katherine Parry 2021-03-24 21:51:17 +0000
  • 385ce9a8f9 Added BPTYPE to coremark_bare config Teo Ene 2021-03-24 16:38:29 -0500
  • a99c0502e5 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. Ross Thompson 2021-03-24 15:56:55 -0500
  • 11109e5a88 Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. Ross Thompson 2021-03-24 13:03:43 -0500
  • d67e28bf50 re-organize privileged tests to be in rv64p to rv32p folders Domenico Ottolia 2021-03-24 13:51:25 -0400
  • c1fe16b70b Give some cache mem inputs a better name Jarred Allen 2021-03-24 12:31:01 -0400
  • d74b6eb69c Updated the .gitignore to reject all the extra compiled objects for the branchmarks. Ross Thompson 2021-03-24 10:30:19 -0500
  • efa8ad4e17 Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack. Ross Thompson 2021-03-24 09:22:21 -0500
  • a51257abca Fix compile errors from const not actually being constant (why does Verilog do this) Jarred Allen 2021-03-24 00:58:56 -0400
  • 1c6e37120e Fixed RAS errors. Still some room for improvement with the BTB and RAS. Ross Thompson 2021-03-23 23:00:44 -0500
  • 4410944049 Merge branch 'main' into cache Jarred Allen 2021-03-23 23:35:36 -0400
  • 84ad1353e4 Fixed a bunch of bugs with the RAS. Ross Thompson 2021-03-23 21:49:16 -0500
  • 56dc8de009 fixed various bugs in the FMA Katherine Parry 2021-03-24 01:35:32 +0000
  • 4fb7a1e0a6 Fixed the valid bit issue. Now the branch predictor is actually predicting instructions. Ross Thompson 2021-03-23 20:20:23 -0500
  • 49348d734b fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. Ross Thompson 2021-03-23 20:06:45 -0500
  • 95dbc5f1fa fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. Ross Thompson 2021-03-23 16:53:48 -0500
  • d6ecc3ede0 Begin work on direct-mapped cache Jarred Allen 2021-03-23 17:03:02 -0400
  • ef3d2dda48 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem Teo Ene 2021-03-23 15:21:13 -0500
  • 174557ae89 Simulation definitely shows the branch predictor counters and branch predictor don't work. :( Ross Thompson 2021-03-23 14:04:58 -0500
  • 5edc90b1c2 added a whole bunch of interseting test code for branches which does not work. Ross Thompson 2021-03-23 13:54:29 -0500
  • 6a050219d4 updated the branch predictor config. Ross Thompson 2021-03-23 12:12:16 -0500
  • 9e61481414 Added first benchmark. Ross Thompson 2021-03-23 12:01:57 -0500
  • 2b0f7cdd42 Temporary exe2memfile0.pl script to support starting addresses of 0. Ross Thompson 2021-03-23 11:53:39 -0500
  • e1842c8da6 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. Ross Thompson 2021-03-23 11:16:28 -0500
  • 69e5319675 busybear: more progress Noah Boorstin 2021-03-23 14:49:26 -0400
  • 1d6a2989ed PC counts branch instructions Shreya Sanghai 2021-03-23 14:25:51 -0400
  • 0d05c51af9 Remove deleted signal from waves Jarred Allen 2021-03-23 14:17:01 -0400
  • 24e403bc35 busybear: more progress moving from instrf to instrrawd Noah Boorstin 2021-03-23 14:06:21 -0400
  • f3194c6388 busybear: ignore illegal instruction when starting Noah Boorstin 2021-03-23 13:28:44 -0400
  • 7da8af4c68 Another tweak to regression-wally.py comments Jarred Allen 2021-03-23 00:18:38 -0400
  • 0f8fe8fb3b Document some internal signals Jarred Allen 2021-03-23 00:10:35 -0400
  • 6ffa01cc4d Add comments explaining icache inputs Jarred Allen 2021-03-23 00:07:39 -0400
  • 82de84469f Slight change to regression-wally.py comments Jarred Allen 2021-03-23 00:01:45 -0400
  • 827993598d Small commit to see if new hook tests non-main branch Jarred Allen 2021-03-22 23:57:01 -0400
  • d5bd5fa9d7 start migrating busybear over to InstrRawD/PCD Noah Boorstin 2021-03-22 23:45:02 -0400
  • 15474f678d Merge branch 'main' into cache Noah Boorstin 2021-03-22 23:28:30 -0400
  • 849641f31e busybear: add better warning on illegal instruction Noah Boorstin 2021-03-22 18:24:31 -0400
  • 34b8f750ce busybear: temporarially force rf[5] correct after failure to read CSR Noah Boorstin 2021-03-22 18:12:41 -0400
  • 77dd0b4504 busybear: allow overwriting read values Noah Boorstin 2021-03-22 17:28:39 -0400
  • 7bb31c3287 busybear: finally get the right error Noah Boorstin 2021-03-22 16:52:22 -0400
  • 5efd5958e7 added delays to uart AHB signals bbracker 2021-03-22 15:40:29 -0400
  • 6ce52f9b80 Remove DelaySideD since it isn't needed Jarred Allen 2021-03-22 15:13:23 -0400
  • b871bfe714 Update icache interface Jarred Allen 2021-03-22 15:04:46 -0400
  • 2aa76b27e1 busybear: comment out some debug printing Noah Boorstin 2021-03-22 14:54:05 -0400
  • 3f897bbf53 Merge branch 'main' into cache Jarred Allen 2021-03-22 14:50:22 -0400
  • 74bcd9b994 regression: expect 200k instead of 100k busybear instrs Noah Boorstin 2021-03-22 14:47:43 -0400
  • 3748d03adc Merge branch 'main' into cache Jarred Allen 2021-03-22 13:47:48 -0400
  • 11d4a8ab34 first pass at PLIC interface bbracker 2021-03-22 10:14:21 -0400
  • f741ba7702 fixed various bugs in the FMA Katherine Parry 2021-03-21 22:53:04 +0000
  • 5b1db9b6a2 Change busybear testbench to reflect new location of InstrF Jarred Allen 2021-03-20 18:20:27 -0400
  • 097e8edb3d Put Imperas testbench back Jarred Allen 2021-03-20 18:19:51 -0400
  • f9cf05a7d4 Fix bug with PC incrementing Jarred Allen 2021-03-20 18:06:03 -0400
  • a3a646d1a9 Merge branch 'main' into cache Jarred Allen 2021-03-20 17:56:25 -0400
  • a2bf5ac202 Fix another bug in the icache (why so many of them?) Jarred Allen 2021-03-20 17:54:40 -0400
  • c5f99c4a34 Revert "Change flop to listen to StallF" Jarred Allen 2021-03-20 17:34:19 -0400
  • b63bfc7afa Fix conflicts in ahb-waves that snuck through manual merging Jarred Allen 2021-03-20 17:16:50 -0400
  • c8028710a5 Change flop to listen to StallF Jarred Allen 2021-03-20 17:04:13 -0400
  • e317e7511e messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic Katherine Parry 2021-03-20 02:05:16 +0000
  • 279c09b27c Merge changes from main Jarred Allen 2021-03-18 18:58:10 -0400
  • 2a29def21c Add icache's read request to ahb wavs Jarred Allen 2021-03-18 18:52:03 -0400
  • 85363e941d AHB bugfixes and sim waveview refactoring bbracker 2021-03-18 18:25:12 -0400
  • 98e93a63c0 maybe AHB works now bbracker 2021-03-18 17:47:00 -0400
  • 09faa40eb6 fixed minor bugs in testbench Shreya Sanghai 2021-03-18 17:37:10 -0400