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  • 90ccd60790 simplify flopenrc's that didn't actually need to be flopenrc's bbracker 2021-10-10 12:25:05 -0700
  • 43d92f2507 Divider cleanup David Harris 2021-10-10 12:24:44 -0700
  • 6704e37597 Simplifying divider FSM David Harris 2021-10-10 12:21:43 -0700
  • 4deae8019a Simplifying divider FSM David Harris 2021-10-10 12:21:36 -0700
  • 2759f1fcb1 Moved & ~StallM from FSM into DivStartE David Harris 2021-10-10 11:49:32 -0700
  • 635fe181f8 Moved divide iteration register names to M stage David Harris 2021-10-10 11:30:53 -0700
  • b713b6ca87 Simplified remainder for divide by 0 David Harris 2021-10-10 11:20:07 -0700
  • 6988c8c37c divider control signal simplificaiton David Harris 2021-10-10 10:55:02 -0700
  • c2bb0324c6 Removed negedge flops from divider David Harris 2021-10-10 10:41:13 -0700
  • 2f02287f91 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-10-10 10:10:06 -0700
  • a88ae5aaff use correct string formatting function bbracker 2021-10-10 10:09:59 -0700
  • 3aa9e088c8 Simplified divider sign handling David Harris 2021-10-10 08:35:26 -0700
  • 39bbeefa78 renamed DivStart David Harris 2021-10-10 08:32:04 -0700
  • 64ed267825 renamed DivSigned David Harris 2021-10-10 08:30:19 -0700
  • 77fe00947e FMA matches diagram and lint warnings fixed Katherine Parry 2021-10-09 17:38:10 -0700
  • 6fce53d146 make testbench-linux halt on some discrepancies with QEMUw bbracker 2021-10-09 17:22:30 -0700
  • 96565f9435 rename adder in fpu for synthesis kipmacsaigoren 2021-10-08 17:47:54 -0500
  • 7fde7aae6e Merging new changes into the old one's I've made in the OKstate servers kipmacsaigoren 2021-10-08 17:47:11 -0500
  • 303beaa083 updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully. Kip Macsai-Goren 2021-10-08 15:40:18 -0700
  • f3058f94c6 removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. Kip Macsai-Goren 2021-10-08 15:33:18 -0700
  • d1c2191b1e updated pmpaddr values, test library to remove unused and unneeded tests. Kip Macsai-Goren 2021-10-08 15:29:32 -0700
  • 2d4623b49c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main kipmacsaigoren 2021-10-08 12:01:44 -0500
  • 3d0383c154 moved fp vectors into vectors subdirectory David Harris 2021-10-07 23:28:06 -0400
  • 6dd85b80a2 Included TestFloat and SoftFloat David Harris 2021-10-07 23:03:45 -0400
  • 55f6584e62 update wave-do bbracker 2021-10-07 19:16:52 -0400
  • 5d60a3a9df update linux wave-do bbracker 2021-10-07 19:15:11 -0400
  • 1824b2af13 fix div restarting bug bbracker 2021-10-07 18:55:00 -0400
  • 28e147bb19 update scripts James E. Stine 2021-10-07 15:14:54 -0500
  • f799a3f5e0 more checkpoint reformatting bbracker 2021-10-07 04:27:45 -0400
  • 76b551cdb3 don't log rf[0] to checkpoint bbracker 2021-10-07 00:58:33 -0400
  • 91d9b6800b update linker scripts to look for vmlinux files bbracker 2021-10-06 16:55:38 -0400
  • a5fbc36864 update linker scripts to look for vmlinux files bbracker 2021-10-06 16:51:31 -0400
  • 8429078d4f TV for conversion and compare James E. Stine 2021-10-06 14:38:32 -0500
  • 199ce88b39 Add generic wave command file James E. Stine 2021-10-06 13:17:49 -0500
  • 49bec73593 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main James E. Stine 2021-10-06 13:16:49 -0500
  • 93668b5185 Update to testbench for FP stuff James E. Stine 2021-10-06 13:16:38 -0500
  • c3e5e3720b Removed instances of <U+200B> character from synth script Teo Ene 2021-10-06 13:11:09 -0500
  • 8db7ce002d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main kipmacsaigoren 2021-10-06 11:52:34 -0500
  • 2afa6e7a6e Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included James E. Stine 2021-10-06 08:56:01 -0500
  • a91c0c8fc7 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat James E. Stine 2021-10-06 08:26:09 -0500
  • 5bcae393c9 added delayed MIP signal Skylar Litz 2021-10-04 18:23:31 -0400
  • b72e94badf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main kipmacsaigoren 2021-10-04 12:28:03 -0500
  • 047bbcf3d7 updated fpga wavefile. Ross Thompson 2021-10-03 12:14:22 -0500
  • e9135f1fd5 Added fpga wave file. Ross Thompson 2021-10-03 11:56:11 -0500
  • 8653a87e24 Added more debug flags. Ross Thompson 2021-10-03 11:41:21 -0500
  • 36bbf0c502 Divider cleaup David Harris 2021-10-03 11:22:34 -0400
  • 10ef563211 Divider cleanup David Harris 2021-10-03 11:16:48 -0400
  • 78eba19a1f Replacing XE and DE with SrcAE and SrcBE in divider David Harris 2021-10-03 11:11:53 -0400
  • 48e33c79a9 Reduced cycle count for DIVW/DIVUW by two David Harris 2021-10-03 09:42:22 -0400
  • 648cc8ef64 Divider comments cleanup David Harris 2021-10-03 01:12:40 -0400
  • 2ae51d1852 Parameterized number of bits per cycle for integer division David Harris 2021-10-03 01:10:15 -0400
  • d468357c24 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-03 00:43:47 -0400
  • 81601e26a3 Divider cleanup David Harris 2021-10-03 00:41:41 -0400
  • c690a863b5 Added suffixes to more divider signals David Harris 2021-10-03 00:32:58 -0400
  • 7fdb0158d4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-10-03 00:30:49 -0400
  • bb868f7a37 checkpoint generator bugfixes bbracker 2021-10-03 00:30:04 -0400
  • 0c08a7c05c More divider cleanup David Harris 2021-10-03 00:20:35 -0400
  • 5e6b2490cb Eliminated extra inversion for subtraction in divider David Harris 2021-10-03 00:10:12 -0400
  • 418e9cd6e6 Added more pipeline stage suffixes to divider David Harris 2021-10-03 00:06:57 -0400
  • b3bded9e6c Added more pipeline stage suffixes to divider David Harris 2021-10-02 22:54:01 -0400
  • 5db800fac3 Divider mostly cleaned up David Harris 2021-10-02 21:10:35 -0400
  • 3a85c972b6 Partial divider cleanup 3 David Harris 2021-10-02 21:00:13 -0400
  • 5d64f04752 Partial divider cleanup 2 David Harris 2021-10-02 20:57:54 -0400
  • f913305993 Partial divider cleanup David Harris 2021-10-02 20:55:37 -0400
  • afd6babc13 Divider code cleanup David Harris 2021-10-02 10:41:09 -0400
  • e33ef58e67 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division David Harris 2021-10-02 10:36:51 -0400
  • 4926ae343a Divider code cleanup David Harris 2021-10-02 10:13:49 -0400
  • 852eb24731 Moved negating divider otuput to M stage David Harris 2021-10-02 10:03:02 -0400
  • 9d63aa683f Moved muldiv result selection to M stage for performance David Harris 2021-10-02 09:38:02 -0400
  • fbe6e41169 Divide performs 2 steps per cycle David Harris 2021-10-02 09:19:25 -0400
  • e11c565a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-09-30 23:15:34 -0400
  • 6aa79657ed Revert "first attempt at verilog side of checkpoint functionality" bbracker 2021-09-30 20:45:26 -0400
  • caa36f267d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-09-30 20:07:43 -0400
  • 9d8e7f2714 Integer Divide/Rem passing all regression. David Harris 2021-09-30 20:07:22 -0400
  • 760f4d66dd RV32 div/rem working signed and unsigned David Harris 2021-09-30 15:24:43 -0400
  • fca9b9e593 Movied tristate to test bench level. Ross Thompson 2021-09-30 11:27:42 -0500
  • cefbcd1b0c Partially sd card read on fpga. Ross Thompson 2021-09-30 11:23:09 -0500
  • 42d573be57 SRT Division unsigned passing Imperas tests David Harris 2021-09-30 12:17:24 -0400
  • fec96218f6 first attempt at verilog side of checkpoint functionality bbracker 2021-09-28 23:17:58 -0400
  • a835572836 first attemtpt at checkpoint infrastructure bbracker 2021-09-28 22:33:47 -0400
  • 7ca801113e Added debugging directives to system verilog. Ross Thompson 2021-09-27 13:57:46 -0500
  • 7117c0493c condense testbench code; debug_level of 0 means don't check at all bbracker 2021-09-27 03:03:11 -0400
  • 7d749b201b added support to due partial fpga simulation. Ross Thompson 2021-09-26 15:00:00 -0500
  • 4d1b02c068 Merge branch 'main' into fpga Ross Thompson 2021-09-26 13:22:53 -0500
  • 3a9bc1e8c1 Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies the flash card to dram. Fixed latch issue in the sd card reader. Ross Thompson 2021-09-26 13:22:23 -0500
  • af53657eaf Merge branch 'sdc' into fpga Ross Thompson 2021-09-25 19:33:07 -0500
  • a213ecbdb2 GPIO marker to indicate the sdc to dram transfer complete. Ross Thompson 2021-09-25 19:29:15 -0500
  • c917f14b6b Almost done writting driver for flash card reader. Ross Thompson 2021-09-25 19:05:07 -0500
  • 69674f272a We now have a rough sdc read routine. Ross Thompson 2021-09-25 17:51:38 -0500
  • 10b46981ff Updated ignore file. Ross Thompson 2021-09-24 18:48:45 -0500
  • 23425c8d71 Write of the SDC address register is correct. The command register is not yet working. The root problem is the command register needs to be reset at the end of the SDC transaction. Ross Thompson 2021-09-24 18:48:11 -0500
  • 86524a5f64 Now have software interacting with the initialization and settting the address register. Ross Thompson 2021-09-24 18:30:26 -0500
  • 44196af61a Have program which checks for sdc init and issues read, but read done is not correctly being read back by the software. The error is in how the sdc indicates busy. Ross Thompson 2021-09-24 15:53:38 -0500
  • 052b8b97fd updated pmp outputs with new exectuaion tests Kip Macsai-Goren 2021-09-24 16:30:16 -0400
  • 57fbd75ae3 updated execute tests, light cleanup, privilege mode changes still need fix. Kip Macsai-Goren 2021-09-24 16:29:56 -0400
  • 9784fc139c updated test library to include: simpler execution tests, widths for each read/write, outputs for pmpaddr writes. Kip Macsai-Goren 2021-09-24 16:28:53 -0400
  • 9ace858a19 completed and cleaned up pmp tests, including execute tests Kip Macsai-Goren 2021-09-24 16:18:44 -0400
  • 17c62b7d5a Fixed lint errors in the SDC. Ross Thompson 2021-09-24 12:38:48 -0500
  • 4f7bc1be48 Added either the sdModel or constant driver for the SDC ports in all test benches. Ross Thompson 2021-09-24 12:31:51 -0500
  • 80e37d2291 Added SDC defines to each config mode. Added sd_top which is the sd card reader. Ross Thompson 2021-09-24 12:24:30 -0500