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  • e0ff7564f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-29 21:39:57 -0600
  • d474caf24f Removed WAdr from cacheway as it is redundant. Ross Thompson 2021-12-29 21:39:43 -0600
  • 7765178a04 Rename of dcache interface signals. Ross Thompson 2021-12-29 21:26:15 -0600
  • c54d81ab04 Fixed generate statement name in csrm for buildroot regression David Harris 2021-12-30 03:01:21 +0000
  • f441c8e16a Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot. David Harris 2021-12-30 02:38:42 +0000
  • 23985eda0a erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-30 02:25:48 +0000
  • d8ba97cf71 RV32ic tests running for simple machine with no privileged unit David Harris 2021-12-30 02:25:46 +0000
  • fd341eda04 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-29 20:18:06 -0600
  • dd81076671 Fixed lint issues with SDC. Ross Thompson 2021-12-29 20:18:00 -0600
  • 5ac170cb3a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-30 00:53:44 +0000
  • 98aaa970dd rv32i regression and linting David Harris 2021-12-30 00:53:39 +0000
  • 30562bcada all FCVT imperas tests pass Katherine Parry 2021-12-30 00:19:40 +0000
  • 12eeda900b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-29 17:56:58 -0600
  • a16b97cfb4 Added default to busfsm. Ross Thompson 2021-12-29 17:53:24 -0600
  • 50b43d3d64 .gitmodule added dirty riscv-arch-test David Harris 2021-12-29 23:50:17 +0000
  • 916d62fa02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-29 23:49:16 +0000
  • 90ccc94e5e Moved lsu interlock fpm to separate module. Ross Thompson 2021-12-29 17:40:24 -0600
  • 81741925aa Moved LSU Bus interface control path into it's own module. Ross Thompson 2021-12-29 17:12:20 -0600
  • 0782e5c5a6 Moved LSU Bus interface control path into it's own module. Ross Thompson 2021-12-29 17:12:20 -0600
  • 1730f644af Name cleanup in LSU. Ross Thompson 2021-12-29 16:34:35 -0600
  • 050523487c Changed names of lsu address signals. Ross Thompson 2021-12-29 15:03:34 -0600
  • 846ed35e20 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-29 14:48:16 -0600
  • b1116600fe Added more generates around virtual memory and csrs in the lsu. Ross Thompson 2021-12-29 14:48:09 -0600
  • d0c0d633a1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-12-29 19:42:35 +0000
  • d2e6bb5674 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main James E. Stine 2021-12-29 13:01:27 -0600
  • 15d38f8c7f Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines James E. Stine 2021-12-29 12:59:17 -0600
  • 3bd9343013 Fixed .gitignore David Harris 2021-12-29 18:58:36 +0000
  • a320fcfeb9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-29 18:53:13 +0000
  • 81b382e51e Switched riscv-arch-test to current hash David Harris 2021-12-29 18:52:52 +0000
  • bc437cf7e0 Cleaned up some names in dcache and lsu. Ross Thompson 2021-12-29 11:21:44 -0600
  • fe22d4544f Converted mux4 to mux3 in dcache. Ross Thompson 2021-12-29 10:58:02 -0600
  • 0c88ddeb5a Simplified the dcache to bus address generation. Ross Thompson 2021-12-29 10:44:37 -0600
  • 6052a69ba7 Fixed interrupt delay bug by reverting CommittedM changes. Ross Thompson 2021-12-28 22:27:12 -0600
  • 86b5a46ab3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-28 21:28:12 -0600
  • 1894afd0d8 Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters. Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop. Ross Thompson 2021-12-28 21:28:03 -0600
  • f9ab193ca8 Added partially working MMU tests David Harris 2021-12-29 03:14:16 +0000
  • 71c069a25d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-28 20:22:36 -0600
  • e4b4800189 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-29 00:29:12 +0000
  • 52a38c5856 Added performance counting to sumtest and added imperas32/64periph to testbench. David Harris 2021-12-29 00:28:51 +0000
  • 76d1dc1721 LSU Bus FSM beautification. Ross Thompson 2021-12-28 16:48:08 -0600
  • e29803be30 Removed CommittedM as it is redundant with LSUStall. Ross Thompson 2021-12-28 16:14:10 -0600
  • 39bd78c295 Changed the bus name between dcache and ebu. Ross Thompson 2021-12-28 15:57:36 -0600
  • d62cd1f701 Reverted changes to subwordread while keeping the new names of the i/o. Ross Thompson 2021-12-28 15:57:21 -0600
  • 9c190b019b Name changes for states in LSU. Ross Thompson 2021-12-28 15:03:24 -0600
  • 13b4201198 Added generate around virtual memory hardware in LSU. Ross Thompson 2021-12-28 15:00:02 -0600
  • f09b10a393 Moved generate for lrsc to lsu. Ross Thompson 2021-12-28 14:17:18 -0600
  • 73af458eb5 More cleanup of dcache. Ross Thompson 2021-12-28 14:12:18 -0600
  • 0e86e5d9f1 Additional cleanup of the LSU. Ross Thompson 2021-12-28 13:59:07 -0600
  • 1e76c24f26 Major cleanup of the LSU. Ross Thompson 2021-12-28 13:10:45 -0600
  • 79b17c5b55 Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw. Ross Thompson 2021-12-28 12:11:45 -0600
  • 34c11ca8d5 Minor dcache cleanup. Ross Thompson 2021-12-28 11:29:16 -0600
  • 243728d089 Moved all bus logic outside the dcache. Still needs cleanup. Ross Thompson 2021-12-28 11:18:47 -0600
  • 74d636cb53 First cut at moving the dcache bus interface into the LSU. Regression test does not run and there is a lot of cleanup to do. Ross Thompson 2021-12-27 18:12:59 -0600
  • d366a1f50f Moved dcache fetch logic outside the dcache except for the fsm. Ross Thompson 2021-12-27 16:45:49 -0600
  • e3ddcbb11e Partial commit. Moved AMO, SWW, and SWR outside the dcache. Step 1 of separate the fetching logic from the caches. Ross Thompson 2021-12-27 15:56:18 -0600
  • 66ad7ddf1c Added D and F tests to regression David Harris 2021-12-27 04:35:34 +0000
  • 67d5b1bb42 Fixed exe2memfile.pl bug David Harris 2021-12-27 00:44:18 +0000
  • 6e20d011d5 Fixed imperas C tests David Harris 2021-12-26 04:45:06 +0000
  • e6ed1372a7 Incorporated new Imperas tests. f and d tests are failing and c tests are hanging. David Harris 2021-12-26 04:36:53 +0000
  • 48bb534658 Started FIR test code and started incorporating Imperas tests David Harris 2021-12-25 22:39:51 +0000
  • d9e61fad67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-25 06:37:30 -0800
  • 9b491788b2 Checked in Chapter 2 C and assembly examples David Harris 2021-12-25 06:35:36 -0800
  • d9977aa1f1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-23 12:40:42 -0600
  • 7fe70c3cc6 Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages. 1: It simplifies the interactions between the caches and the hptw. 2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process. Ross Thompson 2021-12-23 12:40:22 -0600
  • ba7d116f10 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-12-22 15:41:12 +0000
  • a8c72c08a9 added wallyVirtIO.patch from Ross David Harris 2021-12-22 07:04:47 -0800
  • 4e1ae8c71f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-21 22:38:05 -0600
  • f863bdc495 linux-wave.do changes. Ross Thompson 2021-12-21 22:37:55 -0600
  • 9ab7c18baa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-22 03:59:14 +0000
  • b15707bb84 Fixed directory in Makefile for exe2memfile David Harris 2021-12-22 03:59:08 +0000
  • 6a8e917e06 It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register. Ross Thompson 2021-12-21 15:59:56 -0600
  • 7844d3f064 Fixed bug where the wrong address is read into the icache memory. Ross Thompson 2021-12-21 15:16:00 -0600
  • 8b97aaac3e Fixed complex bug where FENCE is instruction class miss predicted as a taken branch. Ross Thompson 2021-12-21 11:29:28 -0600
  • 3f62a64056 Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE. Ross Thompson 2021-12-20 23:45:55 -0600
  • a157235a4b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-20 23:27:46 -0600
  • ffe792bcfc Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address. Ross Thompson 2021-12-20 23:27:37 -0600
  • b085339303 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-20 21:16:25 -0800
  • 07810f4025 Renamed to setup.sh and fixed path bug David Harris 2021-12-20 21:14:35 -0800
  • e00791a890 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-21 05:10:17 +0000
  • 09a24f7240 Improving Wally installation makefile David Harris 2021-12-21 05:10:14 +0000
  • bf9082b0ad Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-20 21:09:20 -0800
  • 475fa01767 Fixing paths in wally-setup.sh David Harris 2021-12-20 21:08:34 -0800
  • 6acf6257e4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-20 21:26:48 -0600
  • 50b307bc0e Looks like rdtime was accidentally replaced with rrame from a find and replace. Ross Thompson 2021-12-20 21:26:38 -0600
  • 972841717f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-21 02:35:45 +0000
  • 787af4287e Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead David Harris 2021-12-21 02:35:41 +0000
  • 8416cae3fe Fixed Type 5b interaction between dcache and hptw. This is a load concurrent with ITLBMiss. Ross Thompson 2021-12-20 18:33:31 -0600
  • b6d75d453a Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM. Ross Thompson 2021-12-20 10:03:56 -0600
  • beb1988539 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-20 10:03:19 -0600
  • df8bd78679 More signal name cleanup in LSU. Ross Thompson 2021-12-19 22:47:48 -0600
  • 3eb5f33705 Remove verbosity from lsu state machine. Ross Thompson 2021-12-19 22:41:34 -0600
  • d3c3422d12 Rename of SelPTW to SelHPTW. Ross Thompson 2021-12-19 22:24:07 -0600
  • 8feb36b926 Signal renames. Ross Thompson 2021-12-19 22:21:03 -0600
  • dc82d44f9e Hardware reductions in the lsu. Ross Thompson 2021-12-19 22:00:28 -0600
  • dc95896303 Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent. Ross Thompson 2021-12-19 21:36:54 -0600
  • 138da1fefa Removed lsuArb and placed remaining logic in lsu.sv. Removed after itlb walk signal as the dcache no longer has any need for this. Formated lsu.sv Ross Thompson 2021-12-19 21:34:40 -0600
  • cc5c5da8bc Added file showing how to compile riscv toolchain for different extension combinations. Ross Thompson 2021-12-19 20:31:55 -0600
  • 596cc4fde4 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. mv qemu patches to tests directory. Ross Thompson 2021-12-19 20:11:32 -0600
  • a25d541dcf Moved generate of conditional units to hart David Harris 2021-12-19 17:03:57 -0800
  • 3c3bfd055e Moved generate statements for optional units into wallypipelinedhart David Harris 2021-12-19 16:53:41 -0800