Ross Thompson
fea439b84d
SDC to ABHLite interface partially done.
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Added SDC to adrdec and uncore.
2021-09-24 10:45:09 -05:00
Ross Thompson
92ea88c57b
Added clock gater and divider to generate the SDCCLK.
2021-09-23 17:58:50 -05:00
Ross Thompson
3cbbd15763
Partial implementation of SDC AHBLite interface.
2021-09-23 17:45:45 -05:00
Ross Thompson
3473f1e612
Started the AHBLite to SDC interface.
2021-09-22 18:08:38 -05:00
Ross Thompson
ec0d2bc7d7
Initial SD Card reader.
2021-09-22 10:50:29 -05:00
Ross Thompson
221dbe92b2
Fixed the amo on dcache miss cpu stall issue.
2021-09-17 22:15:03 -05:00
Ross Thompson
e16c27225b
Finished adding the d cache flush. Required ensuring the write data, address, and size are
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correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Ross Thompson
cfd522da6b
The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.
2021-09-17 10:33:57 -05:00
Ross Thompson
0b1e59d075
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
348187ea70
Added counters to walk through d cache flush.
2021-09-16 17:12:51 -05:00
Ross Thompson
d901f60a6d
Added flush controls to cachway.
2021-09-16 16:56:48 -05:00
Ross Thompson
cae350abb7
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
9fa048980d
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
David Harris
bbb6c7bef7
Restored old integer divider
2021-09-12 22:07:52 -04:00
David Harris
dd1e7548ed
Modified rxfull determination in UART, started division
2021-09-12 20:00:24 -04:00
Ross Thompson
be864abcc5
Fixed bug with or_rows.
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If ROWS == 1 then the output was always X. Fixed by adding if to check if ROWS==1.
2021-09-11 15:51:11 -05:00
Ross Thompson
570aab4275
Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.
2021-09-11 15:40:27 -05:00
Ross Thompson
5744796431
Fixed dcache to prevent latches in FPGA synthesized design.
2021-09-11 12:03:48 -05:00
Ross Thompson
6f4542f063
Third attempt at fixing the write enables for the icache cacheway.
2021-09-09 15:08:10 -05:00
Ross Thompson
6965bde95c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Refixed some bit width issues in the icache.
2021-09-09 12:44:02 -05:00
Ross Thompson
1d370ca71f
fixed some lint bugs.
2021-09-09 12:38:57 -05:00
David Harris
12bd351edf
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6550f38af9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
bbracker
bb84354a47
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
Ross Thompson
49e75d579c
Set associate icache working, but way 0 is never written.
2021-09-07 12:46:16 -05:00
Ross Thompson
05455f8392
Changed name of memory in icache.
2021-09-06 20:54:52 -05:00
James E. Stine
02a1fda650
Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR
2021-09-03 10:26:38 -05:00
Ross Thompson
2968623f9a
Partial multiway set associative icache.
2021-08-30 10:49:24 -05:00
Katherine Parry
70f332fe2f
FMA cleanup
2021-08-28 10:53:35 -04:00
Ross Thompson
6a9fa2fae3
Fixed bugs I introduced to the icache.
2021-08-27 15:00:40 -05:00
Ross Thompson
d433db3048
Renamed PCMux (icache) to SelAdr to match dcache.
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Removed unused cache files.
2021-08-27 11:14:10 -05:00
Ross Thompson
96cbd8e785
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
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One downside is it increases the icache complexity. However it also fixes an untested bug. If a region
was uncacheable it would have been possible for the request to be made multiple times. Now that is
not possible. Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
Ross Thompson
4ace7fe946
Renamed ICacheCntrl to icachefsm.
2021-08-26 15:57:17 -05:00
Ross Thompson
d6ff89b7e6
Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
2021-08-26 15:43:02 -05:00
Ross Thompson
aea7afead6
Finished moving data path logic from the ICacheCntrl.sv to icache.sv.
2021-08-26 13:06:24 -05:00
Ross Thompson
86fc632790
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
fd28c4f556
Removed unused logic in icache.
2021-08-26 10:49:54 -05:00
Ross Thompson
e4bbd3bbc7
Converted the icache type from logic to state type.
2021-08-26 10:41:42 -05:00
Ross Thompson
91fba80a6d
Additional cleanup of ahblite.
2021-08-25 22:53:20 -05:00
Ross Thompson
8836d91896
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
Ross Thompson
596bc138bc
Forgot to include a few files in the last few commits.
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Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
2021-08-25 22:30:05 -05:00
Ross Thompson
0530047f53
Moved dcache fsm to separate module.
2021-08-25 21:37:10 -05:00
Ross Thompson
d23b860c96
Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
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This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
2021-08-25 21:09:42 -05:00
Ross Thompson
c5e2443298
Replaced dcache generate ORing with or_rows.
2021-08-25 13:46:36 -05:00
Ross Thompson
e5336f4ee1
Rename of DCacheMem to cacheway.
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simplified dcache names.
2021-08-25 13:33:15 -05:00
Ross Thompson
e9a1dc90f6
Removed generate around the dcache memories.
2021-08-25 13:27:26 -05:00
