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8836d91896
cvw
/
wally-pipelined
/
src
History
Ross Thompson
8836d91896
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
..
cache
Forgot to include a few files in the last few commits.
2021-08-25 22:30:05 -05:00
ebu
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
fpu
all conversions go through the execute stage result mux
2021-08-16 13:06:09 -04:00
generic
simplified or_rows generation and renamed oneHotDecoder to onehotdecoder
2021-08-25 06:46:41 -04:00
hazard
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
ieu
Moved the ReadDataW register into the datapath.
2021-07-22 14:52:03 -05:00
ifu
Fixed bug with the compressed immediate generation. Several formats should zero extend.
2021-07-26 11:55:31 -05:00
lsu
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
mmu
partial dcache reorg.
2021-08-25 12:42:05 -05:00
muldiv
Fixed syntax errors in some floating point modules. This came up in
2021-08-15 16:48:49 -05:00
privileged
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
uncore
Modified invalid plic reads to return 0 rather than deadbeaf.
2021-08-11 16:56:22 -05:00
wally
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
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