Katherine Parry
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f5bfdf46db
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fpu unpacking unit created
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2021-07-14 17:56:49 -04:00 |
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bbracker
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335afb14e7
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testvector unlinker for dev purposes
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2021-07-14 11:05:34 -04:00 |
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James Stine
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e6d19be87c
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put back for now to test fdiv
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2021-07-14 06:48:29 -05:00 |
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Abe
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782344cfd9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-14 04:47:31 -04:00 |
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Abe
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ac92823c8d
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Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use
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2021-07-14 04:46:11 -04:00 |
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bbracker
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46e704b7ef
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-14 00:21:39 -04:00 |
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bbracker
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92899b33f8
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make testvector scripts agree with new file structure; use symbols to determine end of linux boot
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2021-07-14 00:21:29 -04:00 |
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bbracker
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28887bb3d5
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needed to create a directory for gdb script
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2021-07-13 19:39:57 -04:00 |
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Abe
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9f9b38db9f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 18:22:36 -04:00 |
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James E. Stine
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46001fef27
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mod 2 of fpdivsqrt update
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2021-07-13 16:59:17 -04:00 |
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James E. Stine
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8382a17969
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Update fpdivsqrt item until move into uarch
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2021-07-13 16:53:20 -04:00 |
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bbracker
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f2bf4920d7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 16:16:04 -04:00 |
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bbracker
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64d22753b5
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changed QEMU to use different ports
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2021-07-13 16:15:51 -04:00 |
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David Harris
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9de97c1e20
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Fixed busybear by restoring InstrValidW needed by testbench
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2021-07-13 14:17:36 -04:00 |
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Abe
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46e1a008c3
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Downloaded clean version of Coremark from EEMBC github page with which to benchmark RISCV-Wally
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2021-07-13 13:37:40 -04:00 |
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David Harris
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2ba82d1a5c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 13:26:51 -04:00 |
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David Harris
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223086ac33
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added or.sv
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2021-07-13 13:26:40 -04:00 |
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Katherine Parry
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ca19b2e215
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Fixed writting MStatus FS bits
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2021-07-13 13:22:04 -04:00 |
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Katherine Parry
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efdec72df1
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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David Harris
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93d6688c3c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 13:19:24 -04:00 |
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David Harris
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b5dddec858
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Fixed InstrValid from W to M stage for CSR performance counters
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2021-07-13 13:19:13 -04:00 |
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bbracker
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3565580f40
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updated buildroot make procedure to incorporate configs more robustly
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2021-07-13 12:40:14 -04:00 |
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bbracker
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99587f58f7
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whoops I accidentally made main.config into a symbolic link; now it is a source file
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2021-07-13 11:00:01 -04:00 |
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bbracker
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fab906821a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 10:04:13 -04:00 |
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bbracker
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4b615c1564
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working config for a buildroot that boots
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2021-07-13 10:04:09 -04:00 |
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David Harris
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861ef5e1cb
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Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
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2021-07-13 09:32:02 -04:00 |
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Katherine Parry
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f3ac46df86
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fcvt.sv cleanup
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2021-07-11 21:30:01 -04:00 |
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Katherine Parry
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36f59f3c99
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Almost all convert instructions pass Imperas tests
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2021-07-11 18:06:33 -04:00 |
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bbracker
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6bd0ca673c
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rootfs.cpio no longer overlaps
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2021-07-11 05:11:12 -04:00 |
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bbracker
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feaeeaf6ac
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greatly stripped down unused stuff in linux config
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2021-07-10 11:53:35 -04:00 |
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David Harris
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20f2a4e47c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-09 19:18:35 -04:00 |
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David Harris
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d3ab6b192a
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added missing tlbmixer.sv
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2021-07-09 19:18:23 -04:00 |
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bbracker
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3be73695e3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-09 18:56:28 -04:00 |
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bbracker
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2a54f6f242
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fix_mem.py bugfix
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2021-07-09 18:56:17 -04:00 |
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bbracker
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1f52a2f938
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organize/update buildroot scripts for new image
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2021-07-09 17:03:47 -04:00 |
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David Harris
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39bd7e7edc
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-09 07:53:30 -04:00 |
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David Harris
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5c2f774c35
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Simplified tlbmixer mux to and-or
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2021-07-08 23:34:24 -04:00 |
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David Harris
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74b6d13195
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Fixed missing stall in InstrRet counter
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2021-07-08 20:08:04 -04:00 |
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bbracker
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44a48cf28d
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organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
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2021-07-08 19:18:11 -04:00 |
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David Harris
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4f1a85ca7c
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Eliminate reserved bits from TLB RAM
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2021-07-08 17:35:00 -04:00 |
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David Harris
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38772de21f
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Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
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2021-07-08 16:58:11 -04:00 |
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David Harris
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1190729896
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TLB cleanup to match diagrams
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2021-07-08 16:52:06 -04:00 |
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David Harris
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5d5274ec73
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-07 06:32:29 -04:00 |
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David Harris
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2bab3f769b
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Renamed tlb ReadLines to Matches
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2021-07-07 06:32:26 -04:00 |
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Abe
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84711fbdc8
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Updated MISA defining as well as porting sizes for peripherals (34 to 56)
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2021-07-07 02:37:09 -04:00 |
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Abe
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c721341691
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Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time.
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2021-07-07 02:28:11 -04:00 |
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Abe
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b536065ee8
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Removed debugging loop to test timers for clarity
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2021-07-06 23:37:43 -04:00 |
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Abe
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8dc40e988e
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Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120
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2021-07-06 23:35:47 -04:00 |
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Abe
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b757c96b2d
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Changed SvMode to SVMode on line 76
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2021-07-06 23:28:58 -04:00 |
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David Harris
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af619dcd75
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Added ASID matching for CAM
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2021-07-06 18:56:25 -04:00 |
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