davidharrishmc
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db8d5d58e4
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Added instructions for rv64i_m/D
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2021-10-30 07:34:53 -07:00 |
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David Harris
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360930fe8b
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Fixed exe2memfile parsing of weird line in arch64d test
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2021-10-30 07:26:18 -07:00 |
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David Harris
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bd1a4769ab
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-29 22:32:08 -07:00 |
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David Harris
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247f247ad3
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tesgen cleanup, added riscv-arch-test D tests
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2021-10-29 22:31:48 -07:00 |
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David Harris
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14b9b8126e
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rearranging testgen
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2021-10-29 22:28:37 -07:00 |
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Ross Thompson
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fba07cf4fa
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-29 12:46:23 -05:00 |
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Ross Thompson
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9c875d38a9
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Fixed the 4 way set associative pseudo LRU replacement policy.
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2021-10-29 12:46:02 -05:00 |
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kipmacsaigoren
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90c85e398b
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added missing destination for copy command
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2021-10-29 11:46:18 -05:00 |
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Ross Thompson
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41dbb59e24
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Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
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2021-10-29 11:03:37 -05:00 |
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kipmacsaigoren
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d7b1fd080e
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added timing through redundant multiplier to mdu timing report.
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2021-10-28 22:43:58 -05:00 |
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kipmacsaigoren
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5d7da0ae77
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made make also save the netlist and log file to outputs
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2021-10-28 22:37:25 -05:00 |
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Ross Thompson
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35fcadbe7f
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Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
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2021-10-28 11:07:18 -05:00 |
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bbracker
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7158bf1d4f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-27 14:40:31 -07:00 |
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bbracker
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ab711c498d
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checkpoint generator off-by-one error fix
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2021-10-27 14:10:29 -07:00 |
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slmnemo
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56813ea496
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Added instructions to enable buildroot tests and updated some paths in README.md
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2021-10-27 13:45:56 -07:00 |
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Noah Limpert
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27251a9935
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Have replaced .* with signal names in ifu
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2021-10-27 13:45:37 -07:00 |
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koooo142857
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33f5de0f5c
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aligned all files in ifu folder
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2021-10-27 12:43:55 -07:00 |
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David Harris
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7df4b0c8e7
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commented out some failing FPU tests
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2021-10-27 11:27:34 -07:00 |
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David Harris
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5ceb778914
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-27 11:03:00 -07:00 |
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David Harris
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582c2bf37b
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Fixed FResultSelM to select proper flags
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2021-10-27 11:02:42 -07:00 |
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davidharrishmc
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33b8d31c39
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Added instructions for making rv32if device
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2021-10-27 10:41:37 -07:00 |
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David Harris
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589bee5875
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-27 10:37:46 -07:00 |
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David Harris
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5783e47e1a
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Changes for floating point sims
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2021-10-27 10:37:35 -07:00 |
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Ross Thompson
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7627e177df
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-27 09:59:55 -05:00 |
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Ross Thompson
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c4170ece27
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Replaced async reset flip flops with sync reset flip flops in cache and bpread.
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2021-10-27 09:57:11 -05:00 |
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Ross Thompson
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400670cb06
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Linux now boots fpga.
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2021-10-26 16:49:16 -05:00 |
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bbracker
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c457fc6e27
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-26 12:43:48 -07:00 |
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bbracker
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1591a40f68
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bugfix argument passing to GDB script; remove outdated GDB script
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2021-10-26 12:43:42 -07:00 |
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David Harris
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b7b6d6f23f
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removed unused signal from wave.do
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2021-10-26 09:02:22 -07:00 |
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David Harris
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90cf37b881
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commented out nonworking tests
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2021-10-26 08:56:49 -07:00 |
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David Harris
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67adc1d7d5
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removed referenc outputs
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2021-10-26 08:51:49 -07:00 |
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David Harris
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426a43f77b
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Forgot to save cacheway merge
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2021-10-26 08:38:13 -07:00 |
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David Harris
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c0145c0a35
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merging changes
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2021-10-26 08:34:36 -07:00 |
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David Harris
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8287a1ef3e
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Synchronous reset in non-flop blocks
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2021-10-26 08:30:35 -07:00 |
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Ross Thompson
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c43b19120f
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Fixed another critical path in the caches.
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2021-10-25 22:05:11 -05:00 |
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Ross Thompson
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1228dbbebc
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Fixed the timing issue in the cache replacement polcy.
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2021-10-25 18:00:23 -05:00 |
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Ross Thompson
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576383c74b
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Fixed bug with the changes to sram1rw.
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2021-10-25 16:11:41 -05:00 |
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Ross Thompson
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f0beb4357a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-25 15:36:21 -05:00 |
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Ross Thompson
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5fd3f7f2c7
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Possible fix for critical path timing in caches.
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2021-10-25 15:33:33 -05:00 |
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bbracker
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66e53929ce
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adapt testbench linux to use reset_ext
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2021-10-25 13:26:44 -07:00 |
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bbracker
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787b54dffc
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copy / link to checkpoint 8500000 dir
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2021-10-25 13:24:02 -07:00 |
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Ross Thompson
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81054d9168
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Fixed issue with dtim (fpga) external abhlite select not triggering.
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
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2021-10-25 14:51:54 -05:00 |
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bbracker
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39efadf2cf
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-25 12:25:37 -07:00 |
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bbracker
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8c4e6baf48
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change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
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2021-10-25 12:25:32 -07:00 |
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Ross Thompson
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32f0b97cd3
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Updated uncore to use sdc.
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
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2021-10-25 14:07:44 -05:00 |
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David Harris
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fbee4963da
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Converted flops to synchronous reset now that reset signal is synchronized
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2021-10-25 11:49:20 -07:00 |
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David Harris
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2bf51362e2
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Added synchronizer to reset
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2021-10-25 10:05:41 -07:00 |
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bbracker
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9b98a499d7
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some linux testbench cleanup
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2021-10-25 10:04:30 -07:00 |
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Ross Thompson
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110d9d3a15
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Fixed synthesize script to find the flops after moving.
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2021-10-25 09:43:07 -05:00 |
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Ross Thompson
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76bba541a7
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Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.
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2021-10-24 21:21:49 -05:00 |
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