12 Commits

Author	SHA1	Message	Date
bbracker	64e0fe4c5a	whoops MTIMECMP is always 64 bits	2021-07-19 15:40:53 -04:00
bbracker	cd469035be	make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset	2021-07-19 15:13:03 -04:00
David Harris	67e191c6f3	Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries	2021-07-04 11:39:59 -04:00
bbracker	5a661a7392	provide time and timeh CSRs based on CLINT's counter	2021-06-17 08:38:30 -04:00
bbracker	7b98e7aa2f	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
Ross Thompson	294f01cbd8	fixed the mtime register.	2021-06-11 13:50:13 -05:00
bbracker	f4fb546969	clint HREADY signal update	2021-03-12 20:23:55 -05:00
bbracker	0f4a231543	first merge of ahb fix	2021-03-05 14:24:22 -05:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	24f767a404	Retimed peripherals for AHB interface	2021-02-26 00:55:41 -05:00
David Harris	817f81c356	Debugging Bus interface	2021-02-22 13:48:30 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00