Ross Thompson
ee81cfff0c
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
9886ed3028
Comments for dcache and icache refactoring.
2021-12-14 14:46:29 -06:00
slmnemo
021faaf8cd
Removed .* from mmu instance inside lsu.sv.
2021-12-08 00:15:30 -08:00
Ross Thompson
705572f0ac
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
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If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
Ross Thompson
8a51fe76c1
Partial cleanup of unused signals in caches and bpred.
2021-10-24 15:04:20 -05:00
David Harris
c9e9cd4a60
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
2cfbd888fd
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
62a23fe878
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
8e516e6391
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
c316bff15a
subword read and csrc lint cleanup
2021-10-23 09:29:15 -07:00
Ross Thompson
e16c27225b
Finished adding the d cache flush. Required ensuring the write data, address, and size are
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correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Ross Thompson
615fd41e7b
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
8836d91896
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
Ross Thompson
596bc138bc
Forgot to include a few files in the last few commits.
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Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
2021-08-25 22:30:05 -05:00
Ross Thompson
814fd80b0f
Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate.
2021-08-12 13:36:33 -05:00
Ross Thompson
67c1028862
Dcache and LSU clean up.
2021-08-10 13:36:21 -05:00
Ross Thompson
60177b92a6
Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.
2021-07-25 23:14:28 -05:00
Ross Thompson
3e916da36e
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
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In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Ross Thompson
551e3491af
Moved the ReadDataW register into the datapath.
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The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
9c90b4bdf7
Fixed bug with the itlb fault not dcache ptw ready state to ready state.
2021-07-22 14:04:56 -05:00
Ross Thompson
313bc5255c
Improved address bus names and usages in the walker, dcache, and tlbs.
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Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
365485bd8b
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
Ross Thompson
4d53b9002f
Broken.
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Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
8317be5aed
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
David Harris
c75d70126f
LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall
2021-07-18 03:51:30 -04:00
Ross Thompson
009c5314b4
Fixed LRSC in 64bit version. 32bit version is broken.
2021-07-17 20:58:49 -05:00
David Harris
8bdf1eaf0f
added lrsc.sv
2021-07-17 21:15:08 -04:00
David Harris
8d348dacce
Started atomics
2021-07-17 21:11:41 -04:00
David Harris
574f7d9c32
moved subwordread to lsu
2021-07-17 20:37:20 -04:00
David Harris
9a86fc899b
LSU cleanup
2021-07-17 20:01:03 -04:00
David Harris
d9750c16a5
Pushing HPTWPAdrM flop into LSUArb
2021-07-17 19:39:18 -04:00
David Harris
fc88b3a693
Continued Translation Address Cleanup
2021-07-17 19:09:13 -04:00
David Harris
6536ef8dce
Refining address interface between HPTW and LSU
2021-07-17 19:02:18 -04:00
David Harris
2f81e4c70d
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:22:24 -04:00
David Harris
a855e0170e
hptw: Propagating PageTableEntryF removal through LSU
2021-07-17 15:01:01 -04:00
David Harris
d4eeabe355
hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE
2021-07-17 14:48:44 -04:00
David Harris
87aa527de7
hptw: minor cleanup
2021-07-17 13:40:12 -04:00
David Harris
b65788d165
Replaced separate PageTypeF and PageTypeM with common PageType
2021-07-17 02:31:23 -04:00
Ross Thompson
0b3dc288ec
Made furture progress in the mmu tests.
2021-07-16 15:56:06 -05:00
Ross Thompson
6521d2b468
Also changed the shadow ram's dcache copy widths.
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Merge branch 'dcache' into main
2021-07-16 14:21:09 -05:00
Ross Thompson
46bce70e42
Fixed walker fault interaction with dcache.
2021-07-16 12:22:13 -05:00
Ross Thompson
e0f719d513
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
2021-07-16 11:12:57 -05:00
Ross Thompson
e5d624c1fa
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
8610ef204c
Renamed DCacheStall to LSUStall in hart and hazard.
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Added missing logic in lsu.
2021-07-15 10:16:16 -05:00
Ross Thompson
ba1e1ec231
Finally have the ptw correctly walking through the dcache to update the itlb.
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Still not working fully.
2021-07-14 22:26:07 -05:00
Ross Thompson
2c946a282f
Fixed d cache not honoring StallW for uncache writes and reads.
2021-07-14 17:23:28 -05:00
Ross Thompson
e91501985c
Routed CommittedM and PendingInterruptM through the lsu arb.
2021-07-14 16:18:09 -05:00
