David Harris
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ecce1e62ee
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changed ideal memory to MEM_DTIM and MEM_ITIM
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2021-12-14 13:05:32 -08:00 |
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Ross Thompson
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4cea8d1a29
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Performance counters now output of coremark.
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2021-12-09 14:48:17 -06:00 |
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Ross Thompson
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b03ca464f1
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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Ross Thompson
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de4ea16d32
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Merge branch 'main' into fpga
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2021-10-20 16:24:55 -05:00 |
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Shreya Sanghai
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4424006624
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added DESIGN_COMPLIER to forgotten config files
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2021-10-12 10:14:04 -07:00 |
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Ross Thompson
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f6c6cb9ed2
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Merge branch 'main' into fpga
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2021-10-11 18:17:58 -05:00 |
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David Harris
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2ae51d1852
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Parameterized number of bits per cycle for integer division
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2021-10-03 01:10:15 -04:00 |
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Ross Thompson
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7ca801113e
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Added debugging directives to system verilog.
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2021-09-27 13:57:46 -05:00 |
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Ross Thompson
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80e37d2291
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Added SDC defines to each config mode.
Added sd_top which is the sd card reader.
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2021-09-24 12:24:30 -05:00 |
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David Harris
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9ae25b0cea
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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c749d08542
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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David Harris
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e1a1a8395e
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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David Harris
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4d40b5faef
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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Abe
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84711fbdc8
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Updated MISA defining as well as porting sizes for peripherals (34 to 56)
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2021-07-07 02:37:09 -04:00 |
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David Harris
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80666f0a71
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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Abe
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a0a4b09c94
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Updated directory coremark_bare's wally-config file to define PMP_ENTRIES
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2021-06-18 11:46:25 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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679e507cc6
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Added SUPPORTED to each peripheral in each config file
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2021-06-17 21:36:32 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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Kip Macsai-Goren
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a95a7a7b82
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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David Harris
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a26bf37be8
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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David Harris
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0674f5506e
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moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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Kip Macsai-Goren
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40cfa86935
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Edited and added constants to support SV48
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2021-06-01 17:49:45 -04:00 |
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Elizabeth Hedenberg
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2d1d929485
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coremark print statment
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2021-05-03 19:35:08 -04:00 |
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Ross Thompson
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72363f5c66
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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Ross Thompson
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6e803b724e
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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Noah Boorstin
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6954e6df4c
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buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
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2021-04-17 14:44:32 -04:00 |
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Thomas Fleming
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303c2c4839
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Implement support for superpages
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2021-04-08 02:44:59 -04:00 |
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bbracker
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31c6b2d01f
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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Teo Ene
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7c364a26e9
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Updated MISA in coremark_bare config file
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2021-03-31 20:39:02 -05:00 |
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Ross Thompson
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a64a37d702
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Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
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2021-03-30 23:18:20 -05:00 |
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Teo Ene
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385ce9a8f9
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Added BPTYPE to coremark_bare config
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2021-03-24 16:38:29 -05:00 |
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bbracker
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11d4a8ab34
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first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
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Noah Boorstin
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bc1a0c6ee7
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
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Noah Boorstin
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a2b0af460e
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everyone gets a bootram
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2021-03-18 12:35:37 -04:00 |
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Teo Ene
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d72d774a0b
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addition to last commit
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2021-03-17 14:52:31 -05:00 |
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Elizabeth Hedenberg
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d0ddb5f461
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replicating coremark changes into coremark bare
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2021-03-17 14:36:34 -04:00 |
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Teo Ene
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396dc61564
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Linux CoreMark and baremetal CoreMark split into two separate tests/configs
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2021-03-04 07:44:33 -06:00 |
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