David Harris
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ea2aa469a1
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hptw: Simplifed out AnyTLBMiss
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2021-07-17 12:07:51 -04:00 |
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David Harris
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784e6cf538
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hptw: Renamed Memstore to MemWrite
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2021-07-17 12:01:43 -04:00 |
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David Harris
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0a6622a6fb
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hptw: Merged RV32/64 FSMs
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2021-07-17 11:55:24 -04:00 |
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David Harris
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cf0975c937
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hptw: FSM simplification
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2021-07-17 11:41:43 -04:00 |
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David Harris
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4469b5a4b3
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hptw: default state should be unreachable
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2021-07-17 11:33:16 -04:00 |
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David Harris
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9cee6c2281
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hptw: factored Misaligned
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2021-07-17 11:31:16 -04:00 |
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David Harris
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fa12727bbb
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hptw: factored HPTWRead
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2021-07-17 11:25:59 -04:00 |
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David Harris
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708f8cc3a2
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hptw: factored HPTWRead
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2021-07-17 11:25:52 -04:00 |
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David Harris
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ef63e1ab52
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hptw: factored pregen
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2021-07-17 11:11:10 -04:00 |
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David Harris
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880aa1c03a
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HPTW: more cleanup
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2021-07-17 04:55:01 -04:00 |
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David Harris
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a0f6c9aec1
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HPTW: factored out DTLBWrite/ITLBWrite
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2021-07-17 04:44:23 -04:00 |
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David Harris
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08e494dd7d
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HPTW: factored out PageTableENtry
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2021-07-17 04:40:01 -04:00 |
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David Harris
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bd270acdb6
|
more cleaning up FSM
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2021-07-17 04:35:51 -04:00 |
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David Harris
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6d8a6eeba0
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cleaning up FSM
|
2021-07-17 04:26:41 -04:00 |
|
David Harris
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330e500442
|
Simplify FSM
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2021-07-17 04:12:31 -04:00 |
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David Harris
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03ef3f7f17
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Pulled TranslationPAdr mux out of HPTW FSM
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2021-07-17 04:06:26 -04:00 |
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David Harris
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5698433463
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Simplified bad PTE detection
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2021-07-17 03:30:17 -04:00 |
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David Harris
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ac67342dd4
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Pulled out shared PTEReg
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2021-07-17 03:21:09 -04:00 |
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David Harris
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86ca9abe42
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Flip-flop clean-up
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2021-07-17 03:15:47 -04:00 |
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David Harris
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9a15a2f7df
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Flip-flop clean-up
|
2021-07-17 03:12:24 -04:00 |
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David Harris
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8241dd4599
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Flip-flop clean-up
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2021-07-17 03:10:17 -04:00 |
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David Harris
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a8a5fa4b3c
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Started pagetablewalker cleanup: combined state flops shared for both RV versions
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2021-07-17 02:53:52 -04:00 |
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David Harris
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b65788d165
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Replaced separate PageTypeF and PageTypeM with common PageType
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2021-07-17 02:31:23 -04:00 |
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David Harris
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dac22d5016
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Removed more unused signals from ahblite
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2021-07-17 02:21:54 -04:00 |
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David Harris
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a898bbb991
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Removed rest of HRDATAW from ahblite
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2021-07-17 02:15:24 -04:00 |
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David Harris
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a19d3f126f
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Commented out HRDATAW logic in ebu
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2021-07-17 02:10:57 -04:00 |
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David Harris
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e3dc59c5a2
|
renamed or_rows.sv
|
2021-07-16 20:17:03 -04:00 |
|
Ross Thompson
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0b3dc288ec
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Made furture progress in the mmu tests.
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2021-07-16 15:56:06 -05:00 |
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Ross Thompson
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6521d2b468
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Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
|
2021-07-16 14:21:09 -05:00 |
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Ross Thompson
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46bce70e42
|
Fixed walker fault interaction with dcache.
|
2021-07-16 12:22:13 -05:00 |
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Ross Thompson
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e0f719d513
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Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
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2021-07-16 11:12:57 -05:00 |
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Kip Macsai-Goren
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abd5b1c02d
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Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
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2021-07-15 18:30:29 -04:00 |
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Ross Thompson
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e5d624c1fa
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Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
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2021-07-15 11:56:35 -05:00 |
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Ross Thompson
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fa26aec588
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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b9902b0560
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Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
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2021-07-15 11:00:42 -05:00 |
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Ross Thompson
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8610ef204c
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Renamed DCacheStall to LSUStall in hart and hazard.
Added missing logic in lsu.
|
2021-07-15 10:16:16 -05:00 |
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Ross Thompson
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704f4f724e
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dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
|
2021-07-14 23:08:07 -05:00 |
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Ross Thompson
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ba1e1ec231
|
Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
|
2021-07-14 22:26:07 -05:00 |
|
Katherine Parry
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c74d26eea4
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Fixed lint warning
|
2021-07-14 21:24:48 -04:00 |
|
Ross Thompson
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c79650b508
|
Added d cache StallW checks for any time the cache wants to go to STATE_READY.
|
2021-07-14 17:25:50 -05:00 |
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Ross Thompson
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2c946a282f
|
Fixed d cache not honoring StallW for uncache writes and reads.
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2021-07-14 17:23:28 -05:00 |
|
Katherine Parry
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f5bfdf46db
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fpu unpacking unit created
|
2021-07-14 17:56:49 -04:00 |
|
Ross Thompson
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e91501985c
|
Routed CommittedM and PendingInterruptM through the lsu arb.
|
2021-07-14 16:18:09 -05:00 |
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Ross Thompson
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adce800041
|
Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled.
|
2021-07-14 15:47:38 -05:00 |
|
Ross Thompson
|
d78e31e9df
|
Forgot to include one hot decoder.
|
2021-07-14 15:46:52 -05:00 |
|
Ross Thompson
|
f4295ff097
|
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
|
2021-07-14 15:00:33 -05:00 |
|
James Stine
|
e6d19be87c
|
put back for now to test fdiv
|
2021-07-14 06:48:29 -05:00 |
|
Ross Thompson
|
9b756d6a94
|
Implemented uncached reads.
|
2021-07-13 23:03:09 -05:00 |
|
Ross Thompson
|
e8bf502bc2
|
Added CommitedM to data cache output.
|
2021-07-13 22:43:42 -05:00 |
|
Ross Thompson
|
3e57c899a2
|
Partially working changes to support uncached memory access. Not sure what CommitedM is.
|
2021-07-13 17:24:59 -05:00 |
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