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Author	SHA1	Message	Date
Daniel Torres	5d7171f6f8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 11:16:09 -07:00
Daniel Torres	526f70e772	commiting current changes to riscof wally tests	2022-07-22 11:14:04 -07:00
cturek	338f44dfc8	Square root negative exponent handling	2022-07-22 16:45:19 +00:00
slmnemo	12c92a05ff	Added new PLIC and UART tests	2022-07-22 07:12:55 -07:00
slmnemo	49565f944c	Added PLIC and UART tests and new functions to the test library	2022-07-22 07:10:39 -07:00
David Harris	07c946bb04	Reset MSR on read	2022-07-22 04:29:27 +00:00
Daniel Torres	28c61a2191	changed gitignore, updated version of arch tests on main build	2022-07-21 21:10:15 -07:00
Daniel Torres	f1578936b8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 20:59:01 -07:00
Daniel Torres	bd918d37ba	added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64	2022-07-21 20:58:58 -07:00
slmnemo	99dcff80c9	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-21 20:35:52 -07:00
slmnemo	bfa500234d	Fixed UART bug related to parity and MSR/LSR	2022-07-21 20:35:46 -07:00
cturek	c170a8d9b6	Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder	2022-07-22 01:27:08 +00:00
cturek	abe1ff906e	Renamed variables, moved output handling to postprocessor, added remainder handling	2022-07-21 20:45:08 +00:00
Daniel Torres	a17361870f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 12:50:04 -07:00
Daniel Torres	d44ec059d0	made makefile more specific, just incase future additions	2022-07-21 12:50:02 -07:00
Daniel Torres	6e9b4f4075	removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes	2022-07-21 12:47:51 -07:00
Katherine Parry	e330a840b0	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-21 19:38:15 +00:00
Katherine Parry	270216dd02	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
cturek	ddc237f6bc	Division working too	2022-07-21 17:59:10 +00:00
cturek	9c694b887e	Updated Radix2 Sqrt to follow new algorithm	2022-07-21 17:36:21 +00:00
Daniel Torres	dad913cb82	fixed gitmodules	2022-07-21 10:15:13 -07:00
Daniel Torres	f33c6c9455	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 10:14:20 -07:00
Daniel Torres	e9aedfdc53	changed the default branch of embench	2022-07-21 10:14:05 -07:00
Katherine Parry	67c99d3d1a	added input enables and improved forwarding	2022-07-21 01:20:06 +00:00
Katherine Parry	e8c9830b88	turn off 2 word store durring non-fp instructions	2022-07-20 21:57:23 +00:00
Ross Thompson	9868e685a4	Minor cleanup of cache.	2022-07-19 23:04:23 -05:00
Ross Thompson	6c8ac7851e	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Katherine Parry	fb890d621d	moved ctrl signal registers into fctrl, also a lot of code cleaning	2022-07-20 02:27:39 +00:00
cturek	d7e90a7086	divsqrt working for floating point	2022-07-20 02:04:20 +00:00
cturek	f75d1c2eef	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-20 02:00:50 +00:00
cturek	8e66b81821	New radix-2 algorithm implemented and working	2022-07-20 02:00:43 +00:00
David Harris	9d125addfa	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-20 01:49:36 +00:00
David Harris	4c740e1494	Reordered embench Makefile to run size tests first	2022-07-20 01:49:33 +00:00
cturek	db39a05abc	small changes	2022-07-20 01:36:25 +00:00
Katherine Parry	531829f7c8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-19 23:44:41 +00:00
Katherine Parry	afcddf7035	oprimized zeros and replaced complex ?: with always_comb	2022-07-19 23:44:37 +00:00
Daniel Torres	7632ce9ee9	embench no longer launches run automatiacally, need to use make run	2022-07-19 15:16:12 -07:00
Daniel Torres	d33d0d22bd	commented out embench 2.0 tests	2022-07-19 13:36:18 -07:00
Daniel Torres	2c2c8d4d9b	made changes to makefile, now builds fastest version (RV64im) by default. Also removed redundent CFLAG funroll-all-loops (was duplicated)	2022-07-19 13:17:02 -07:00
slmnemo	77f7b179ee	fixed GPIO test by adding a new function to clear PLIC interrupts	2022-07-19 08:59:16 -07:00
Ross Thompson	ffda64587c	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
David Harris	38fac8e05c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-19 02:58:13 +00:00
David Harris	8caab918ec	Removed duplicate -march from CoreMark makefile	2022-07-19 02:58:07 +00:00
Katherine Parry	4c2afbbc4f	moved Se into execute stage	2022-07-19 01:10:10 +00:00
Katherine Parry	a590728350	reworked fmashiftcalc to match book	2022-07-19 00:04:24 +00:00
David Harris	6ec2a5db4a	Coremark cleanup	2022-07-18 16:48:13 -07:00
David Harris	59eb11b73a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 23:11:12 +00:00
David Harris	ab08826b6a	Cleaned up Coremark makefile	2022-07-18 23:10:22 +00:00
Katherine Parry	86f0327f79	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 20:49:01 +00:00
Katherine Parry	e599f82b29	moved Ss to execute stage	2022-07-18 20:48:56 +00:00