27 Commits

Author	SHA1	Message	Date
slmnemo	dc11066ff2	Passed Regression: Seems to work perfectly fine	2022-06-09 18:21:13 -07:00
slmnemo	5a6eae214a	?	2022-06-09 17:50:47 -07:00
slmnemo	3e8d3bae88	Changes made on 9th Jun	2022-06-09 17:33:51 -07:00
slmnemo	81d373c7ab	Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.	2022-06-08 17:34:02 -07:00
slmnemo	11924bdd9b	Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending	2022-06-08 15:59:15 -07:00
slmnemo	e17ee3073e	Fixed ifu displaying LSU bus state in wave.do	2022-06-08 15:30:32 -07:00
slmnemo	315c2f0669	Working version: Fixed error where Word count would always increment even without AHB to bus ACK	2022-06-08 15:29:32 -07:00
slmnemo	054cf5f7b0	Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors	2022-06-08 15:03:15 -07:00
slmnemo	2d76953d42	Added lock signal to ensure AHB speaks with the right bus	2022-06-08 02:19:21 +00:00
slmnemo	73e0c1c07f	Reworked bus to handle burst interfacing	2022-06-07 11:22:53 +00:00
slmnemo	cf05fec9c7	Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access	2022-05-31 16:33:05 -07:00
slmnemo	a86c4d5ff3	Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode	2022-05-31 15:57:55 -07:00
slmnemo	9ad1a42886	Redid the FSM to prepare for burst mode implementation	2022-05-31 15:57:42 -07:00
slmnemo	f78fa3b9b9	Reverted incorrect Ack	2022-05-28 10:06:26 +00:00
slmnemo	bc17f883d4	changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word	2022-05-26 18:41:27 -07:00
slmnemo	847c7930c4	added LSUBurstDone signal to signal when a burst has finished	2022-05-26 16:29:13 -07:00
slmnemo	08430a1e85	added burst size signals to the IFU, EBU, LSU, and busdp	2022-05-25 18:02:50 -07:00
slmnemo	cebf93cf9c	idk lol it says this has an unadded change	2022-05-25 17:17:49 -07:00
slmnemo	af0300c3d7	added documentation for ahblite burst types to ahblite.sv	2022-05-19 18:31:46 -07:00
David Harris	3036de316a	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
David Harris	de5e80696d	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	db2271b7e0	LSU cleanup	2022-01-15 00:11:30 +00:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	1d8451c2cf	Capitalized LSU and IFU, changed MulDiv to MDU	2022-01-07 04:30:00 +00:00
David Harris	32590d484c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00