386 Commits

Author	SHA1	Message	Date
Jarred Allen	d6ecc3ede0	Begin work on direct-mapped cache	2021-03-23 17:03:02 -04:00
Noah Boorstin	69e5319675	busybear: more progress	2021-03-23 14:49:30 -04:00
Jarred Allen	0d05c51af9	Remove deleted signal from waves	2021-03-23 14:17:17 -04:00
Noah Boorstin	24e403bc35	busybear: more progress moving from instrf to instrrawd	2021-03-23 14:06:21 -04:00
Noah Boorstin	f3194c6388	busybear: ignore illegal instruction when starting	2021-03-23 13:28:56 -04:00
Jarred Allen	0f8fe8fb3b	Document some internal signals	2021-03-23 00:10:35 -04:00
Jarred Allen	6ffa01cc4d	Add comments explaining icache inputs	2021-03-23 00:07:39 -04:00
Jarred Allen	827993598d	Small commit to see if new hook tests non-main branch	2021-03-22 23:57:01 -04:00
Noah Boorstin	d5bd5fa9d7	start migrating busybear over to InstrRawD/PCD ... this breaks busybear for now	2021-03-22 23:45:04 -04:00
Noah Boorstin	15474f678d	Merge branch 'main' into cache	2021-03-22 23:28:30 -04:00
Noah Boorstin	849641f31e	busybear: add better warning on illegal instruction ... ...also it seems that mret is being picked up as an illegal instruction??	2021-03-22 18:24:35 -04:00
Noah Boorstin	34b8f750ce	busybear: temporarially force rf[5] correct after failure to read CSR	2021-03-22 18:12:41 -04:00
Noah Boorstin	77dd0b4504	busybear: allow overwriting read values	2021-03-22 17:28:44 -04:00
Noah Boorstin	7bb31c3287	busybear: finally get the right error	2021-03-22 16:52:22 -04:00
bbracker	5efd5958e7	added delays to uart AHB signals	2021-03-22 15:40:29 -04:00
Jarred Allen	6ce52f9b80	Remove DelaySideD since it isn't needed	2021-03-22 15:13:23 -04:00
Jarred Allen	b871bfe714	Update icache interface	2021-03-22 15:04:46 -04:00
Noah Boorstin	2aa76b27e1	busybear: comment out some debug printing	2021-03-22 14:54:05 -04:00
Jarred Allen	3f897bbf53	Merge branch 'main' into cache	2021-03-22 14:50:22 -04:00
Noah Boorstin	74bcd9b994	regression: expect 200k instead of 100k busybear instrs ... and a minor busybear bugfix	2021-03-22 14:47:52 -04:00
Jarred Allen	3748d03adc	Merge branch 'main' into cache	2021-03-22 13:47:48 -04:00
bbracker	11d4a8ab34	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Katherine Parry	f741ba7702	fixed various bugs in the FMA	2021-03-21 22:53:04 +00:00
Jarred Allen	5b1db9b6a2	Change busybear testbench to reflect new location of InstrF	2021-03-20 18:20:27 -04:00
Jarred Allen	097e8edb3d	Put Imperas testbench back	2021-03-20 18:19:51 -04:00
Jarred Allen	f9cf05a7d4	Fix bug with PC incrementing	2021-03-20 18:06:03 -04:00
Jarred Allen	a3a646d1a9	Merge branch 'main' into cache	2021-03-20 17:56:25 -04:00
Jarred Allen	a2bf5ac202	Fix another bug in the icache (why so many of them?)	2021-03-20 17:54:40 -04:00
Jarred Allen	c5f99c4a34	Revert "Change flop to listen to StallF" ... This reverts commit c8028710a5.	2021-03-20 17:34:19 -04:00
Jarred Allen	b63bfc7afa	Fix conflicts in ahb-waves that snuck through manual merging	2021-03-20 17:16:50 -04:00
Jarred Allen	c8028710a5	Change flop to listen to StallF	2021-03-20 17:04:13 -04:00
Katherine Parry	e317e7511e	messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic	2021-03-20 02:05:16 +00:00
Jarred Allen	279c09b27c	Merge changes from main	2021-03-18 18:58:10 -04:00
Jarred Allen	2a29def21c	Add icache's read request to ahb wavs	2021-03-18 18:52:03 -04:00
bbracker	85363e941d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
bbracker	98e93a63c0	maybe AHB works now	2021-03-18 17:47:00 -04:00
Shreya Sanghai	09faa40eb6	fixed minor bugs in testbench	2021-03-18 17:37:10 -04:00
Shreya Sanghai	bbe0957df5	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	1091dd10c1	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00
Ross Thompson	8f4051543c	Fixed minor bug with the size of gshare.	2021-03-18 16:00:09 -05:00
Shreya Sanghai	eb86bfc084	removed unnecesary PC registers in ifu	2021-03-18 16:31:21 -04:00
Thomas Fleming	8d484174a7	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-18 14:36:42 -04:00
Thomas Fleming	7f7597e667	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
Thomas Fleming	7d4906b1c7	Improve page table creation in python file	2021-03-18 14:27:09 -04:00
Noah Boorstin	bc1a0c6ee7	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	a2b0af460e	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Noah Boorstin	ced2a32d21	busybear: update memory map, add GPIO	2021-03-18 12:17:35 -04:00
Teo Ene	57f1ca5259	Switched coremark to RV64IM	2021-03-17 22:39:56 -05:00
Teo Ene	d2fe42d6d0	adapted coremark bare testbench to new dtim RAM HDL	2021-03-17 16:59:02 -05:00
Jarred Allen	e69376c823	Merge branch 'main' into cache ... Conflicts: wally-pipelined/testbench/testbench-imperas.sv	2021-03-17 16:40:52 -04:00