David Harris
3c8eafc8ee
Cleaned bram interface
2022-06-08 01:39:44 +00:00
David Harris
9e5ab4d378
Added ahbapbbridge and cleaning RAM
2022-06-08 01:31:34 +00:00
Katherine Parry
e42afbfb30
paramerterized some small fma units
2022-06-01 23:34:29 +00:00
Katherine Parry
4ed7933aa3
added unpackinput.sv
2022-05-31 16:18:50 +00:00
Katherine Parry
95b506c5e0
some optimizations in unpacker
2022-05-27 11:36:04 -07:00
Katherine Parry
1be91753fe
moved lzc to generic and small optimizations on fcvt
2022-05-27 09:04:02 -07:00
Ross Thompson
91e99f0d34
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-04 10:56:10 -05:00
Ross Thompson
b77201143f
Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.
2022-04-04 10:38:37 -05:00
Ross Thompson
48c49802b2
Fixed linting issues.
2022-04-01 15:20:45 -05:00
Ross Thompson
88c5cdc873
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-31 11:39:41 -05:00
Ross Thompson
bf9683f0d2
Forced to go back to hard coded preload.
2022-03-31 11:39:37 -05:00
Ross Thompson
285fc6fd4d
Modified clint to support all byte write sizes.
2022-03-31 11:31:52 -05:00
Ross Thompson
f52ab01362
Partial cleanup of memories.
2022-03-30 11:09:21 -05:00
Ross Thompson
839bede656
Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
2022-03-30 11:04:15 -05:00
Ross Thompson
66e9380cfb
Partial fix to allow byte write enables with fpga and still get a preload to work.
2022-03-29 19:12:29 -05:00
Ross Thompson
6d914def08
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
396c97fc36
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
David Harris
1479762ae9
RAM simplification
2022-02-08 20:15:23 +00:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
9da1ed4ed9
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
a86a9f5c2a
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
e3136c9a1e
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
7ad2eb009a
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
6a555032eb
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
Ross Thompson
9982549057
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
2b4c81fe98
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
c1d6550ccb
Removed generate statements
2022-01-05 14:35:25 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
