David Harris
2ae51d1852
Parameterized number of bits per cycle for integer division
2021-10-03 01:10:15 -04:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
c749d08542
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
David Harris
e1a1a8395e
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
David Harris
4d40b5faef
Added cache configuration to config files
2021-07-19 18:19:46 -04:00
David Harris
80666f0a71
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
David Harris
9645b023c9
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
bbracker
23f479d225
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
David Harris
35c74348a4
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
David Harris
679e507cc6
Added SUPPORTED to each peripheral in each config file
2021-06-17 21:36:32 -04:00
David Harris
0ffbd03139
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
Kip Macsai-Goren
a95a7a7b82
working version with new mmu comments, old boottim values
2021-06-08 15:20:25 -04:00
David Harris
b613f46c2d
Resized BOOT TIM to 1 KB
2021-06-08 14:04:32 -04:00
David Harris
2ae5ca19b5
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
ff62000e2c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
David Harris
dc0b19dfaa
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Kip Macsai-Goren
22e8e06ac7
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
David Harris
a26bf37be8
Started MMU
2021-06-04 11:59:14 -04:00
David Harris
0674f5506e
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
40cfa86935
Edited and added constants to support SV48
2021-06-01 17:49:45 -04:00
Ross Thompson
ab509614bb
Changed to bp config to use gshare.
2021-06-01 12:14:58 -05:00
Ross Thompson
857f59ab5c
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
Ross Thompson
8a035104ac
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Ross Thompson
7f38056879
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Ross Thompson
72363f5c66
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
c91436d3b7
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
98a04abe6c
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Ross Thompson
bff2d61a1f
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
Shreya Sanghai
b544526766
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Ross Thompson
a64a37d702
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Ross Thompson
6a050219d4
updated the branch predictor config.
2021-03-23 13:54:59 -05:00
Ross Thompson
2b0f7cdd42
Temporary exe2memfile0.pl script to support starting addresses of 0.
2021-03-23 13:54:59 -05:00
