Commit Graph

129 Commits

Author SHA1 Message Date
David Harris
3d13683c07 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Ross Thompson
5b5a615e4a Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
0eceeeeeaa Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
David Harris
e9b314f902 fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression 2022-12-30 06:40:25 -08:00
Cedar Turek
4ed2c6255c idiv passing radix 2, four copies 2022-12-27 22:10:48 -08:00
David Harris
87abed6722 cleanup 2022-12-27 21:29:36 -08:00
David Harris
2de66e9eef Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
7e77a39d32 Restored missing floating point load/store tests 2022-12-25 22:28:14 -08:00
Kip Macsai-Goren
a768d70093 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Ross Thompson
376b01fcb8 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
ebdac1a9d0 Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
cturek
f57211bb49 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Kip Macsai-Goren
f486a763d9 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Kip Macsai-Goren
2dfa426e10 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
c6c0ef05db commented out periph test from wally32 periph so rv32ic doesn't hang 2022-12-05 20:23:16 -08:00
Kip Macsai-Goren
ae32e2a9ee added passing tests to regression 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
282d06b45f added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
128b3d20e7 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
David Harris
9c1b7e53e4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
4c6003d9e2 update test list 2022-12-02 04:28:47 -08:00
David Harris
ed39099405 reorder tests 2022-12-01 16:27:33 -08:00
David Harris
f64c0589fe FPU test list 2022-12-01 10:18:36 -08:00
cturek
e28a6901a9 div tests in sim-wally 2022-11-30 02:32:04 +00:00
Kip Macsai-Goren
26b4147f40 added failing satp invalid tests to regression 2022-11-29 10:43:38 -08:00
cturek
d5c5450f8d Reoredered tests for arch32m 2022-11-09 18:42:00 +00:00
David Harris
c78643f4e4 Reorder embench tests to prevent crash 2022-11-04 15:21:51 -07:00
Ross Thompson
ae7a71c0f4 Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Kip Macsai-Goren
d5cd67cf09 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
a4fc5d3476 Created initial endianness tests 2022-09-16 01:06:26 +00:00
Ross Thompson
6581490f9c Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
DTowersM
f9cbc9cf8e fixed qrduino keyerror in embench test 2022-08-31 00:17:58 +00:00
Ross Thompson
c636387613 Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
2022-08-24 17:52:25 -05:00
Katherine Parry
0f077012c3 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
David Harris
8b8f045491 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
6ee8036ae7 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
e3b970d3ff Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
David Harris
449c80b5f7 More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
539174f6f6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
Daniel Torres
d95b266d49 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
2bbfd67082 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
44c30ec082 fixed error in tests.vh 2022-07-22 14:55:55 -07:00
slmnemo
170601af0b Added UART test to peripheral test 2022-07-22 14:55:34 -07:00
Daniel Torres
fbe3a1af12 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 13:52:19 -07:00
Daniel Torres
261b9aa5a1 commented out embench test that should be commented out 2022-07-22 13:52:13 -07:00
slmnemo
0d98ff74b4 Added PLIC test to regression 2022-07-22 12:35:37 -07:00
slmnemo
49565f944c Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
bd918d37ba added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
6e9b4f4075 removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
Daniel Torres
d33d0d22bd commented out embench 2.0 tests 2022-07-19 13:36:18 -07:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00