Shreya Sanghai
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30bfd7534c
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added branch tests
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2021-02-12 22:40:08 -05:00 |
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Tejus Rao
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5158ca4220
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added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
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2021-02-11 13:38:38 -05:00 |
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ethan-falicov
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9edc4b6bfe
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Fixed merge conflict stuff
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2021-02-10 10:03:30 -05:00 |
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ethan-falicov
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7e8a58de1a
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More merge conflicts yay
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2021-02-10 09:54:30 -05:00 |
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ethan-falicov
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f778f464b7
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Merge conflict fixing
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2021-02-10 09:45:47 -05:00 |
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ethan-falicov
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06541260e0
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Adding I Type test cases from Lab 1
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2021-02-10 09:39:43 -05:00 |
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David Harris
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183a2dcfb5
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Debugging bus interface.
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2021-02-10 01:43:54 -05:00 |
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David Harris
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2357f5513b
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Debugging instruction fetch
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2021-02-09 11:02:17 -05:00 |
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David Harris
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3551cc859b
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Data memory bus integration
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2021-02-07 23:21:55 -05:00 |
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Jarred Allen
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403a0d033c
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Fix compile error in imperas testbench
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2021-02-07 15:48:12 -05:00 |
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Elizabeth Hedenberg
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81a1eb9a74
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merge conflict?
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2021-02-07 02:34:49 -05:00 |
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Jarred Allen
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48ade25577
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Actually run the WALLY-LOAD tests
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2021-02-06 14:56:40 -05:00 |
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bbracker
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691d651fde
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JAL testing
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2021-02-05 08:08:42 -05:00 |
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Thomas Fleming
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8588a1ed6b
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Complete STORE tests
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2021-02-04 15:38:22 -05:00 |
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David Harris
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396cea1ea7
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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David Harris
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9c81278f28
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Added HCLK and HRESETn
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2021-01-30 00:56:12 -05:00 |
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David Harris
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a357f2a0e7
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Connected AHB bus to Uncore
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2021-01-29 23:43:48 -05:00 |
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David Harris
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dc2443c55b
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Moving data memory to uncore
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2021-01-29 15:37:51 -05:00 |
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David Harris
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ed3cb83c10
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Added ahblite bus interface unit
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2021-01-29 01:07:17 -05:00 |
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David Harris
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824014c5c0
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Repartitioned with Instruction Fetch Unit, Integer Execution Unit
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2021-01-27 22:49:47 -05:00 |
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David Harris
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616afaba69
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Moved privileged unit from datapath to hart
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2021-01-27 07:46:52 -05:00 |
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David Harris
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b88508ca11
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Repartitioned datapath and controller into ieu
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2021-01-27 06:40:26 -05:00 |
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David Harris
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fa18052348
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Added test configurations
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2021-01-25 11:28:43 -05:00 |
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