386 Commits

Author	SHA1	Message	Date
David Harris	e4d18f1808	removed more old 64priv tests	2022-03-04 03:57:19 +00:00
bbracker	41c75dc89d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-04 00:12:00 +00:00
bbracker	c3e59ae2df	comment out nonfunctioning CSR-PERMISSIONS-M test	2022-03-04 00:11:55 +00:00
David Harris	a50f1a4424	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-04 00:07:34 +00:00
David Harris	2cea3349ad	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
bbracker	d645666fe7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-04 00:06:27 +00:00
bbracker	79ff8d3c80	remove imperas32p tests	2022-03-04 00:06:18 +00:00
David Harris	6431ad4a8b	Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas	2022-03-03 15:38:08 +00:00
David Harris	f76e396255	erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-02 23:47:16 +00:00
David Harris	8e83aaeced	fma file fixes	2022-03-02 23:47:01 +00:00
bbracker	87aad1d953	fix peripheral test and add it to regression	2022-03-02 23:44:39 +00:00
bbracker	11423d1d17	but apparently QEMU doesn't show UXL in SSTATUS	2022-03-02 22:44:19 +00:00
bbracker	6d7bc928af	update SXL UXL bits in MSTATUS to match new QEMU trace	2022-03-02 22:15:57 +00:00
bbracker	e9e827c83e	add CSRs to waveview	2022-03-02 18:31:10 +00:00
bbracker	4fe35aadf2	add rv32a tests to regression	2022-03-02 17:54:55 +00:00
bbracker	7d7a4fefb3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-02 17:46:40 +00:00
David Harris	c543fedc60	removed imperas-riscv-tests	2022-03-02 17:28:20 +00:00
bbracker	b6031bb15f	fix buildroot checkpointing and add it back to regression	2022-03-02 16:00:19 +00:00
bbracker	29179c6787	add LRSC test and add wally64a to regression	2022-03-02 07:09:37 +00:00
David Harris	0ecfff7e3a	FMA project ready to start	2022-03-01 20:58:08 +00:00
bbracker	d2fa5fa645	buildroot graphical sim bugfix	2022-03-01 03:24:23 +00:00
bbracker	a8e8cfb838	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
bbracker	d8ddda760b	deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test	2022-03-01 00:37:46 +00:00
David Harris	329fea9329	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
David Harris	2ea93c4ac3	adrdecs comments	2022-02-28 20:33:41 +00:00
David Harris	2de31a15da	Modified address decoder for native access to CLINT	2022-02-28 19:13:14 +00:00
David Harris	3a43450ac9	hptw cleanup for synthesis	2022-02-28 05:54:34 +00:00
David Harris	f4be78ecc3	Created softfloat_demo showcasing how to do math with SoftFloat	2022-02-27 18:17:21 +00:00
David Harris	dbd73e8cfd	Moved regression work directories to regression/wkdir to reduce clutter	2022-02-27 17:35:09 +00:00
David Harris	3675a813c6	Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior	2022-02-27 17:23:33 +00:00
David Harris	62d62f9a9e	Moved FMA back into source tree to facilitate synthesis	2022-02-27 15:41:41 +00:00
David Harris	5b15e552c6	Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue	2022-02-27 15:12:10 +00:00
David Harris	c35a071203	Moved fma directory	2022-02-27 14:20:15 +00:00
David Harris	283a25e1a7	fma simulation infrastructure	2022-02-27 04:36:43 +00:00
David Harris	40bc380073	fma passing multiply vectors	2022-02-27 04:36:01 +00:00
David Harris	f29cc4b33f	simplified fma Makefile	2022-02-26 19:55:42 +00:00
David Harris	b2db58e982	Made softfloat.a a symlink	2022-02-26 19:53:04 +00:00
David Harris	a9f9cfa5b6	Added start of fma	2022-02-26 19:51:19 +00:00
David Harris	ff674b695c	Moved Softfloat / TestFloat	2022-02-26 19:17:32 +00:00
Ross Thompson	730fdb029a	Fixed bug with DAPageFault being wrong when HPTW writes not supported.	2022-02-23 10:54:34 -06:00
Ross Thompson	6f53f7943f	More spillsupport more structual.	2022-02-23 10:27:14 -06:00
Ross Thompson	19ec874641	Fixed bug with spill support and Instruction DA Page Faults.	2022-02-23 10:16:12 -06:00
Ross Thompson	15f6871a8d	Added generates to pcnextf muxes for privileged and caches.	2022-02-22 22:45:00 -06:00
Ross Thompson	834b308ed6	Fixed "bug" with wally-pipelined.do	2022-02-22 22:19:25 -06:00
Ross Thompson	59f04f2518	Minor busdp cleanup.	2022-02-22 17:28:26 -06:00
Ross Thompson	ea29291024	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-22 14:45:53 -06:00
Ross Thompson	971dd494f6	Clarified interlockfsm.	2022-02-22 11:31:28 -06:00
bbracker	2322e66f9f	fix lint bugs in PLIC and UART	2022-02-22 05:04:18 +00:00
bbracker	ac114e1c6d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-22 04:27:50 +00:00
bbracker	202bd2f8f8	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00