bbracker
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83a0a37f8e
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make xCOUNTEREN what buildroot expects it to be
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2021-06-20 09:22:31 -04:00 |
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bbracker
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9bc5ddf5f2
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PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable
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2021-06-17 05:19:36 -04:00 |
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David Harris
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49b5fa3994
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Reverted MIDELEG and MEDELEG to XLEN so busybear passes
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2021-06-10 23:47:32 -04:00 |
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David Harris
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01d6ca1e2a
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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David Harris
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90e5781471
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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Thomas Fleming
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ad40464557
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-05-03 23:15:39 -04:00 |
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Domenico Ottolia
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5ab86a690b
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Fix bug that caused stvec to get the wrong value
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2021-05-03 17:54:57 -04:00 |
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Thomas Fleming
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eda5a267ee
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Implement PMP checker and revise PMA checker
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2021-05-03 17:37:42 -04:00 |
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Thomas Fleming
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cfe64e7c24
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
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2021-05-03 14:02:19 -04:00 |
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Domenico Ottolia
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d03ca20dc9
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Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
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2021-04-29 20:42:14 -04:00 |
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Thomas Fleming
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5f2bccd88f
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Clean up PMA checker and begin PMP checker
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2021-04-29 02:20:39 -04:00 |
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Ross Thompson
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6e803b724e
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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Domenico Ottolia
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6b4d2e9634
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Fix misa synthesis bug (for real now)
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2021-04-22 15:35:20 -04:00 |
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Domenico Ottolia
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fb8f244dab
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Fix misa bug
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2021-04-22 00:59:07 -04:00 |
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Domenico Ottolia
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bf86a809eb
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Add tests for sepc register
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2021-04-20 23:50:53 -04:00 |
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Domenico Ottolia
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0c307d2db1
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Fix synthesis warnings for privileged unit (replace 'initial' settings)
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2021-04-20 17:57:56 -04:00 |
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Domenico Ottolia
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65abe13f4f
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Cause an Illegal Instruction Exception when attempting to write readonly CSRs
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2021-04-08 05:12:54 -04:00 |
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Ross Thompson
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a64a37d702
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Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
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2021-03-30 23:18:20 -05:00 |
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Thomas Fleming
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b1d849c822
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Add all PMP addr registers
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2021-03-24 21:58:33 -04:00 |
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Noah Boorstin
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bc1a0c6ee7
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
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Noah Boorstin
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f48af209c4
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busybear: make CSRs only weird for us
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2021-03-05 00:46:32 +00:00 |
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Noah Boorstin
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14cde0d59c
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Change CSR reset and available bits to conform to OVPsim
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
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2021-02-04 22:03:45 +00:00 |
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David Harris
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a44c2abb12
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Minor tweaks
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2021-02-02 19:44:37 -05:00 |
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David Harris
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9d7e242596
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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396cea1ea7
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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