Xavi/cvw
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1920 Commits

Author SHA1 Message Date
eroom1966
d9d5b99218 update 2023-01-19 13:29:46 +00:00
eroom1966
7c0cad148d Partial fix for misaligned LD/ST 2023-01-18 17:11:39 +00:00
eroom1966
2e4e5f9c61 changes made with Ross 2023-01-18 16:46:48 +00:00
eroom1966
a5a5b7a408 add im flags for compressed disass 2023-01-18 13:37:28 +00:00
eroom1966
df4419dea2 remove volatile for FFLAGS and FCSR 2023-01-18 13:33:57 +00:00
eroom1966
c18942bd0b refer to correct path 2023-01-18 13:26:07 +00:00
Ross Thompson
b30c13a188 Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage. 2023-01-17 18:24:46 -06:00
eroom1966
8caa93ce4d refactor all rvvi into single initial block 2023-01-17 13:01:01 +00:00
eroom1966
f4e7e54abe Code refactor and addition of rvvi interface 2023-01-17 12:47:38 +00:00
Ross Thompson
7c4eaa1ca6 Found a potential issue with mstatush when XLEN = 64. 2023-01-16 13:57:28 -06:00
Ross Thompson
fabe13bdce Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs. 2023-01-16 13:35:06 -06:00
Ross Thompson
4aa2b5737f Signal renames for ras. 2023-01-13 15:56:10 -06:00
Ross Thompson
0e215ac3c6 Removed 1 bit from instruction classification. 2023-01-13 15:19:53 -06:00
Ross Thompson
de7f3b14fc More branch predictor cleanup. 
Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
 2023-01-13 12:57:18 -06:00
Ross Thompson
cf608ee45f Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
ea7c447218 Possible minor enhancement to gshare. 2023-01-13 12:32:39 -06:00
Ross Thompson
395b7a5b32 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00
Ross Thompson
ef4c684336 Added supervisor mode registers to tracer. 2023-01-12 17:04:41 -06:00
Ross Thompson
9917be817c Added M CSRs to the CSRArray. 2023-01-12 16:51:51 -06:00
Ross Thompson
a68773eba1 added machine csr to logger. 2023-01-12 16:35:19 -06:00
Ross Thompson
2e622c9860 Added support to print the gprs. 2023-01-12 16:09:30 -06:00
Ross Thompson
4733b787f8 rvvi trace is coming alone nicely. 2023-01-12 14:46:31 -06:00
Ross Thompson
3cc37e3f12 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
2f2f3d6da5 Stripped out all signature checking. 
Removed multiple tests loop.
Only runs 1 test now.
 2023-01-12 12:45:44 -06:00
Ross Thompson
5ad0bacf5b Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
94f24d3f58 Added instruction logger. 2023-01-12 10:09:34 -06:00
Ross Thompson
e0867b1840 Completed review of LSU. 2023-01-11 19:06:03 -06:00
Ross Thompson
aba1df9abf Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 18:52:49 -06:00
Ross Thompson
318ceba34d Improved LSU formating. 2023-01-11 18:52:46 -06:00
sarah-harris
796a189451 privilege unit -> privileged unit in ifu.sv 
privilege unit -> privileged unit in ifu.sv
 2023-01-11 16:33:08 -08:00
Ross Thompson
ad22a9ea02 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:26:11 -06:00
sarah-harris
203cc164d9 Added Sarah.Harris@unlv.edu to alu.sv 
Added Sarah.Harris@unlv.edu to alu.sv
 2023-01-11 15:20:41 -08:00
Ross Thompson
b60e9730a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:15:49 -06:00
David Harris
8c6ddcc15b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
Ross Thompson
bccef3b39c Updated header for LSU. 2023-01-11 17:15:07 -06:00
David Harris
9a057ef5cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 15:13:58 -08:00
Ross Thompson
a8931e0211 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:09:23 -06:00
Katherine Parry
4556839960 fixed typo bug in fpu 2023-01-11 17:07:02 -06:00
Ross Thompson
6999b4562e Updated branch predictor. 2023-01-11 17:00:45 -06:00
David Harris
3ea4dd4898 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
99ff78b902 FPU cleanup 2023-01-11 12:27:00 -08:00
David Harris
4ff2627a50 fpu cleanup 2023-01-11 12:18:06 -08:00
David Harris
d1bfdddd8c Rename FP and FPU to F in signal names 2023-01-11 11:46:36 -08:00
David Harris
15026f61f7 FPU comments 2023-01-11 11:31:28 -08:00
David Harris
654abcde61 Replaced MDUE with IntDivE in FDIVSQRT 2023-01-11 11:06:37 -08:00
David Harris
f6987fab8c Switched to XZeroE from NumerZeroE in square root preprocessor 2023-01-10 12:37:49 -08:00
David Harris
739c2c8322 Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
David Harris
446b5fa83f Division constant cleanup 2023-01-10 11:14:59 -08:00
David Harris
4a34007b49 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-09 13:04:37 -08:00
David Harris
b2ec52c94d Changed DIVN from NF+3 to NF+2, cleanup 2023-01-09 13:04:34 -08:00