bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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e4f4e1bd43
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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839bede656
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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997c1b87fe
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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66e9380cfb
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Kip Macsai-Goren
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d031c003ba
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fixed arch bge test signature output location after update
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2022-03-29 20:45:18 +00:00 |
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Kip Macsai-Goren
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a6d90a25c2
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fixed signature location of the new periph with no compressed instructions
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2022-03-29 02:15:17 +00:00 |
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Skylar Litz
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f91fb7a388
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add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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Kip Macsai-Goren
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7ae1d14191
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added basic trap tests that do not pass regression yet. updated signature adresses
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2022-03-25 22:57:41 +00:00 |
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bbracker
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6f6663cd67
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fix multiple-context PLIC checkpoint generation
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2022-03-25 01:02:22 +00:00 |
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bbracker
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d33de3ef6b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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bbracker
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4b376e2834
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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71aad2d213
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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aa60b57fb3
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Cleanup in testbench-linux.sv.
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2022-03-22 22:34:38 -05:00 |
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Ross Thompson
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b2487f4b72
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-22 21:28:50 -05:00 |
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Ross Thompson
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4ca9458534
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added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
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2022-03-22 21:28:34 -05:00 |
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Ross Thompson
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e6b42cb10f
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Added spoof of uart addresses +0x2 and +0x6.
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2022-03-22 16:52:27 -05:00 |
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Katherine Parry
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e3d01c875b
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FMA parameterized and FMA testbench reworked
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2022-03-19 19:39:03 +00:00 |
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Ross Thompson
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7a25d577ba
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Added new asserts to testbench.
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2022-03-11 15:41:53 -06:00 |
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bbracker
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742e8d98cd
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fix up PLIC and UART checkpointing
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2022-03-07 23:48:47 -08:00 |
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bbracker
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92e1583db5
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change testbench-linux.sv to use new shared location of disassembly files
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2022-03-07 20:04:08 -08:00 |
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David Harris
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e4d18f1808
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removed more old 64priv tests
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2022-03-04 03:57:19 +00:00 |
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bbracker
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c3e59ae2df
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comment out nonfunctioning CSR-PERMISSIONS-M test
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2022-03-04 00:11:55 +00:00 |
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bbracker
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79ff8d3c80
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remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
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bbracker
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87aad1d953
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fix peripheral test and add it to regression
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2022-03-02 23:44:39 +00:00 |
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bbracker
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4fe35aadf2
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add rv32a tests to regression
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2022-03-02 17:54:55 +00:00 |
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bbracker
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b6031bb15f
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fix buildroot checkpointing and add it back to regression
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2022-03-02 16:00:19 +00:00 |
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bbracker
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29179c6787
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add LRSC test and add wally64a to regression
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2022-03-02 07:09:37 +00:00 |
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bbracker
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a8e8cfb838
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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bbracker
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d8ddda760b
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deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
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2022-03-01 00:37:46 +00:00 |
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David Harris
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329fea9329
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Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
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2022-02-28 20:50:51 +00:00 |
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bbracker
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ac114e1c6d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-02-22 04:27:50 +00:00 |
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bbracker
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202bd2f8f8
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Kip Macsai-Goren
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04892c5d38
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added scratch register tests for 64 and 32 bits
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2022-02-21 07:03:12 +00:00 |
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Kip Macsai-Goren
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324efa7d42
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added 32 bit pma tests to regression even though they've been working fo a while
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2022-02-18 19:43:24 +00:00 |
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Kip Macsai-Goren
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dcb5d0f6a9
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Added misa test for both 32 and 64 bits
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2022-02-18 19:41:50 +00:00 |
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Kip Macsai-Goren
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e16581d73d
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added CSR permission and minfor to 32 bit tests
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2022-02-15 20:19:14 +00:00 |
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Kip Macsai-Goren
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943c4d9d7c
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merged test macros in with 32 bit tests
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2022-02-15 20:19:14 +00:00 |
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David Harris
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f734afb866
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Just needed to recompile - all good. Now removed uretM because N-mode is depricated
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2022-02-15 19:48:49 +00:00 |
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Kip Macsai-Goren
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9ff4025844
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light cleanup for privileged tests
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2022-02-15 17:06:16 +00:00 |
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David Harris
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64e9f4c0d3
|
Restored E tests to makefrag
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2022-02-08 16:41:11 +00:00 |
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David Harris
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f00b3ac27e
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Fixed TIM tests; rv32e test still failing
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2022-02-08 15:24:37 +00:00 |
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David Harris
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76dccbad91
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Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail
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2022-02-08 12:40:02 +00:00 |
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David Harris
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c61cd55c5c
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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David Harris
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cbef88ec10
|
Lab 3 file cleanup
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2022-02-08 10:26:37 +00:00 |
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Kip Macsai-Goren
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0eb280b314
|
added new tests to make and testbench
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2022-02-06 19:47:22 +00:00 |
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bbracker
|
f67af23bf3
|
remove sporadic tabs from tests.vh so that it is now only spaces
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2022-02-05 23:07:38 +00:00 |
|
David Harris
|
72bc64ef28
|
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
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2022-02-05 04:16:18 +00:00 |
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David Harris
|
2c67f32b97
|
RV32e tests
|
2022-02-04 14:30:36 +00:00 |
|
David Harris
|
a6708ed887
|
cache cleanup
|
2022-02-03 15:36:11 +00:00 |
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