19 Commits

Author	SHA1	Message	Date
David Harris	e3dc59c5a2	renamed or_rows.sv	2021-07-16 20:17:03 -04:00
Ross Thompson	fa26aec588	Merge branch 'main' into dcache	2021-07-15 11:55:20 -05:00
Ross Thompson	d78e31e9df	Forgot to include one hot decoder.	2021-07-14 15:46:52 -05:00
David Harris	223086ac33	added or.sv	2021-07-13 13:26:40 -04:00
David Harris	b23192cf1b	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
David Harris	9645b023c9	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
Teo Ene	ec21126474	Flow updated for 90nm	2021-07-01 13:32:42 -05:00
David Harris	1ec90a5e1f	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
Katherine Parry	75a6097467	fixed lint warnings for fpu and lzd	2021-06-05 12:06:33 -04:00
Ross Thompson	e50a1ef5e4	Fixed a few lint errors, ... clock gater was wrong, missing signal definitions in branch predictor.	2021-06-02 09:33:24 -05:00
Ross Thompson	0670c57fd2	The clock gater was not implemented correctly. Now it is level sensitive to a low clock.	2021-06-01 15:05:22 -05:00
Ross Thompson	fe22fd2db8	added clock gater to floating point divider to speed up simulation time.	2021-06-01 13:46:21 -05:00
James E. Stine	12c34c25f3	Modify elements of generics for LZD and shifter wrote for integer ... divider.	2021-05-31 08:36:19 -04:00
Noah Boorstin	2c25e270a2	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
David Harris	2543c29839	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00