David Harris
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b3a13a01f8
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Stripped write capaibilty out of rom_ahb
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2022-08-24 17:23:08 -07:00 |
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David Harris
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e6077f1f16
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Added ROM module and moved memories into generic/mem
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2022-08-24 17:03:22 -07:00 |
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David Harris
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1ef0c7c2be
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-24 16:30:28 -07:00 |
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David Harris
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9d5468887e
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Ram cleanup
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2022-08-24 16:30:25 -07:00 |
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Ross Thompson
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22e989ac7b
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No longer need wally-pipelined-fpga.do.
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2022-08-24 18:10:45 -05:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c636387613
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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07b2858890
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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012559169b
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Fixed lint errors with bram wrapper.
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2022-08-24 13:19:23 -05:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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e2138d8d0f
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bram synthesis test
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2022-08-23 19:34:45 -07:00 |
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David Harris
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b8cc06a434
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-24 00:09:20 +00:00 |
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David Harris
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a1311c06ef
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Rolled back synth scripts to fff91ae commit before Madeleine's modifications to write config files; the modified version is failing right away with trouble copying configs
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2022-08-24 00:09:16 +00:00 |
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Ross Thompson
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0c52c7f69c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 18:52:15 -05:00 |
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Ross Thompson
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ee3d968da0
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Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.
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2022-08-23 18:51:11 -05:00 |
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David Harris
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8d48ff4e63
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Fixed FPU-IEU forwarding stall
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2022-08-23 14:14:41 -07:00 |
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David Harris
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8b2e368805
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Only stall FPU to IEU on convert instructions with dependencies
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2022-08-23 12:57:18 -07:00 |
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David Harris
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113258a0d0
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Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
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2022-08-23 12:17:19 -07:00 |
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David Harris
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69be6d0873
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Simplify IEU-FP datapath
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2022-08-23 11:16:36 -07:00 |
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David Harris
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746842107b
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Improved illegal instruction checking in FPU
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2022-08-23 11:08:02 -07:00 |
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David Harris
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27cca2e3fd
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Fixed LSU typos
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2022-08-23 10:23:08 -07:00 |
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David Harris
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46f30d3dbe
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 10:14:59 -07:00 |
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David Harris
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13831aa3d3
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typo in srtfsm
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2022-08-23 10:14:54 -07:00 |
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Katherine Parry
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f9aa94f87b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-23 16:36:32 +00:00 |
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Katherine Parry
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72a54ef621
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renamed rounding bits to L,G,R,S and fixed lint warning
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2022-08-23 16:36:20 +00:00 |
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Ross Thompson
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1f74528792
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 11:15:04 -05:00 |
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Ross Thompson
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7080fe7788
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Reversed order of supported sized in adrdecs.
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2022-08-23 11:14:53 -05:00 |
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Ross Thompson
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b0606a1699
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Replaced FPU data replicaiton on WriteData bus with 0 extention.
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2022-08-23 10:46:03 -05:00 |
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Ross Thompson
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b9fadc11c3
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Replaced LSU data replication with 0 extention.
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2022-08-23 10:43:47 -05:00 |
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Ross Thompson
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cd0da2e3b3
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Updated the names of the *WriteDataM inside the LSU to more meaningful names.
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
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2022-08-23 10:34:39 -05:00 |
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David Harris
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9e3d13ca52
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Q depends on D
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2022-08-23 08:29:59 -07:00 |
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David Harris
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7c91ed38a3
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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David Harris
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b795cf4731
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Updated testbench assertions.
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2022-08-23 07:23:24 -07:00 |
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David Harris
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a9a5285ba8
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Named HTRANS states in busfsm
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2022-08-22 13:56:46 -07:00 |
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David Harris
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24a05c35d9
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Renamed signals for LSU - FPU interface
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2022-08-22 13:47:56 -07:00 |
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David Harris
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13d863a810
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renamed GrantData to LSUGrant
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2022-08-22 13:47:19 -07:00 |
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David Harris
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34eece10b8
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Finished FPU-LSU interface cleanup
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2022-08-22 13:43:04 -07:00 |
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David Harris
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7151befd04
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Removed FStore2 and simplified HPTW
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2022-08-22 13:29:54 -07:00 |
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David Harris
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bf54c1c868
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Simplified FPU-LSU interface to skip IEU
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2022-08-22 13:29:20 -07:00 |
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David Harris
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fffad8b314
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-22 13:28:54 -07:00 |
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David Harris
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2170203847
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Simplified FPU-LSU interface to skip IEU
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2022-08-22 13:28:51 -07:00 |
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Katherine Parry
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a1f0c6c598
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-22 17:16:25 +00:00 |
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Katherine Parry
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1accb92745
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sqrt passes - lint warnings remain
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2022-08-22 17:16:12 +00:00 |
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David Harris
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564281b8c1
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Removed 2-cycle FPU-IEU latency stall
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2022-08-22 16:14:15 +00:00 |
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David Harris
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1404d1c248
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moved CSA to generic
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2022-08-22 08:41:23 +00:00 |
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David Harris
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a8870b70b2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-22 08:28:31 +00:00 |
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David Harris
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b91f33372e
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Commented out unused comparators
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2022-08-22 08:28:28 +00:00 |
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Ross Thompson
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88d34d0f56
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-21 16:03:11 -05:00 |
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Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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92c3cdc27d
|
Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
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2022-08-21 15:28:29 -05:00 |
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