Daniel Torres
|
9a2e7bcd64
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-17 15:50:10 -07:00 |
|
Daniel Torres
|
dcdd3702c3
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
3a5c02b44a
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
Madeleine Masser-Frye
|
ab7c936788
|
remove run deletion with wally synthesis
|
2022-06-17 19:45:38 +00:00 |
|
Madeleine Masser-Frye
|
a89e689520
|
error calculation function, fixed energy units
|
2022-06-17 19:36:32 +00:00 |
|
Madeleine Masser-Frye
|
12b76e4fe2
|
latest synths and synth script
|
2022-06-17 19:34:58 +00:00 |
|
David Harris
|
7e4988c2de
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-17 15:45:24 +00:00 |
|
Daniel Torres
|
aa05dd7636
|
added new work files to gitignore
|
2022-06-16 18:06:25 -07:00 |
|
Daniel Torres
|
311427532c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-16 18:05:18 -07:00 |
|
Daniel Torres
|
cf55b7edc0
|
added files needed for arch to build
|
2022-06-16 18:05:06 -07:00 |
|
Katherine Parry
|
8425f8838d
|
hopefully fixed lint error
|
2022-06-17 00:14:39 +00:00 |
|
Katherine Parry
|
93906b9457
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-15 22:58:42 +00:00 |
|
Katherine Parry
|
e121dcd4af
|
postprocess out of fpu critical path
|
2022-06-15 22:58:33 +00:00 |
|
Madeleine Masser-Frye
|
c2493168b6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-15 18:30:27 +00:00 |
|
Madeleine Masser-Frye
|
76e30ed8ab
|
cleanup, plots for paper
|
2022-06-15 18:28:36 +00:00 |
|
Madeleine Masser-Frye
|
d23d5d12f2
|
fresh set of syntheses
|
2022-06-15 18:26:16 +00:00 |
|
James Stine
|
d69a8f4077
|
Add back SV for integer division to use 8-bit CPA in qslc
|
2022-06-15 11:46:39 -05:00 |
|
James Stine
|
535a9a04ee
|
Add r=4 C code
|
2022-06-15 11:44:09 -05:00 |
|
Katherine Parry
|
11b252a735
|
some synth fpu optimizations
|
2022-06-14 23:58:39 +00:00 |
|
David Harris
|
ecd733942a
|
Removed testbench.sv.bak
|
2022-06-14 22:04:38 +00:00 |
|
DTowersM
|
a0d6f948b8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-14 17:08:48 +00:00 |
|
DTowersM
|
2023a2af2c
|
fixed a typo in makefile
|
2022-06-14 17:08:39 +00:00 |
|
Katherine Parry
|
998876ce49
|
removed false critical path from fpu
|
2022-06-14 16:50:46 +00:00 |
|
Katherine Parry
|
566001e07b
|
fixed acciedental critical path in FPU
|
2022-06-14 00:02:38 +00:00 |
|
DTowersM
|
919c1818a8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 23:34:35 +00:00 |
|
DTowersM
|
3d8cf0c0a7
|
fixed typo in git ignore
|
2022-06-13 23:34:27 +00:00 |
|
DTowersM
|
8178a6732b
|
added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo
|
2022-06-13 23:33:10 +00:00 |
|
DTowersM
|
1f4d56ba32
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
|
Katherine Parry
|
31fd8772cf
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
David Harris
|
8ea484a343
|
Cleanup on RAM module
|
2022-06-13 19:37:43 +00:00 |
|
David Harris
|
b7a7ca6eac
|
Typo in gpio reset
|
2022-06-13 19:37:05 +00:00 |
|
slmnemo
|
eb41185a70
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-13 12:30:33 -07:00 |
|
David Harris
|
be65e8f862
|
Removed SRT testvectors from repo
|
2022-06-13 19:27:33 +00:00 |
|
slmnemo
|
915b8e2adb
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-13 12:27:23 -07:00 |
|
slmnemo
|
7b704f8db0
|
Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
|
2022-06-13 12:26:18 -07:00 |
|
slmnemo
|
98c07ce2c0
|
Added more comments
|
2022-06-13 12:26:08 -07:00 |
|
David Harris
|
ccd16210bc
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 19:26:07 +00:00 |
|
David Harris
|
e9ef9a5cb8
|
Fixed XOR logic in GPIO
|
2022-06-13 19:26:03 +00:00 |
|
slmnemo
|
3d715a098c
|
Added comment about name of LSUBusInit/Lock signal
|
2022-06-13 10:56:02 -07:00 |
|
slmnemo
|
cadd62e49f
|
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
|
2022-06-10 20:43:56 -07:00 |
|
slmnemo
|
beb4317e68
|
Added comments to signals added so the bus is easier to analyze
|
2022-06-10 20:30:04 -07:00 |
|
slmnemo
|
b7357efc6b
|
Fixed failed regression state by only enabling counting when doing cached operations
|
2022-06-10 20:00:09 -07:00 |
|
slmnemo
|
63ed390c90
|
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
|
2022-06-10 19:10:01 -07:00 |
|
Madeleine Masser-Frye
|
422bd2043f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-10 21:11:47 +00:00 |
|
Madeleine Masser-Frye
|
6cf37feb8d
|
equation table, plot adjustments
|
2022-06-10 21:11:39 +00:00 |
|
Madeleine Masser-Frye
|
7cdf9cd4d3
|
added 'd' suffix to muxes for data-critical synths
|
2022-06-10 21:11:05 +00:00 |
|
DTowersM
|
4bbe5eeecd
|
simplified coremark
|
2022-06-10 19:15:17 +00:00 |
|
DTowersM
|
13c1cf12b2
|
added some comments to help debuggers in the future
|
2022-06-10 01:44:52 +00:00 |
|
slmnemo
|
dc11066ff2
|
Passed Regression: Seems to work perfectly fine
|
2022-06-09 18:21:13 -07:00 |
|
slmnemo
|
ec7cdee0f3
|
Merge branch 'main' into cacheburstmode
|
2022-06-09 17:51:03 -07:00 |
|