Jarred Allen
36452749d7
Merge remote-tracking branch 'origin/main' into cache
2021-03-15 19:08:25 -04:00
Noah Boorstin
9e1612c166
remove regression-wally.sh
2021-03-15 19:03:57 -04:00
Ross Thompson
4c8952de6a
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Ross Thompson
806cfc4ea5
Fixed the parallel script so the rv64ic passes.
...
rv32ic and busybear still have issues.
2021-03-15 12:04:59 -05:00
Jarred Allen
926235b180
Merge upstream changes
2021-03-14 14:57:53 -04:00
Jarred Allen
deb13f34bb
Get non-jump case working
2021-03-14 14:46:21 -04:00
Ross Thompson
7ceef2b0c6
Fixed the issue with the batch mode not working after adding the function radix.
2021-03-12 20:16:03 -06:00
Ross Thompson
6ee97830f7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3
Cleanup of the branch predictor flush and stall controls.
2021-03-12 14:57:53 -06:00
Ross Thompson
318b642359
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 17:12:21 -06:00
Noah Boorstin
cc94046084
test regression script: add commented out rv32ic tests
2021-03-11 12:57:54 -05:00
Noah Boorstin
394b79b5de
add rv32ic regression test
2021-03-11 12:40:29 -05:00
Noah Boorstin
54fa16d783
test regression script: parallalize better
2021-03-11 12:25:20 -05:00
Noah Boorstin
aba54659bf
test regression script: try adding verilator checking also
2021-03-11 07:32:31 +00:00
Noah Boorstin
81c14f899d
try adding delays to test regression script
2021-03-11 06:59:50 +00:00
Noah Boorstin
1093b07670
this is just a test for now, try to reimplement regression-wally in bash
2021-03-11 06:45:45 +00:00
Ross Thompson
845115302e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-10 15:37:02 -06:00
Ross Thompson
f92f766573
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Ross Thompson
dcae90e3ad
I finally think I got the function radix debugger working across both 32 and 64 bit applications.
2021-03-10 14:43:44 -06:00
Ross Thompson
50a92247b3
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 11:00:51 -06:00
Jarred Allen
ae9bcc174d
Merge upstream changes
2021-03-09 21:20:34 -05:00
David Harris
c2f340681d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
17c0f9629a
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
c780a25f92
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
1b206d5a3c
busybear: make a second .do file with better optimization for command line mode
2021-03-08 19:35:00 +00:00
Noah Boorstin
93c9c57426
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Ross Thompson
d5f151eb0f
Updated the paths to the branch predictor memory preloads for busy bear.
2021-03-05 15:36:00 -06:00
Ross Thompson
87ed6d510c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Noah Boorstin
3c5be59e9b
busybear: add branch preditor loading to do file
...
(sorry to add more loading to the do instead of less)
2021-03-05 21:01:41 +00:00
Noah Boorstin
86142e764a
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
889d2c0b85
fix wally-pipelined-batch.do to match wally-pipelined.do
2021-03-05 20:27:01 +00:00
bbracker
19fc7d2381
refactored sim file
2021-03-05 14:25:16 -05:00
bbracker
0f4a231543
first merge of ahb fix
2021-03-05 14:24:22 -05:00
Noah Boorstin
5a3ba1174e
busybear: better implenetation of sim-busybear-batch
2021-03-05 00:39:03 +00:00
Noah Boorstin
dfae278ffb
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Jarred Allen
106718b196
Remove rd2, working for non-compressed
2021-03-04 16:46:43 -05:00
Noah Boorstin
827dfd774b
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Teo Ene
37bf3d836f
Updated coremark .do file for easier debugging
2021-03-03 15:10:39 -06:00
Teo Ene
e7f7f980b3
Updated coremark .do file for easier debugging
2021-03-02 17:23:39 -06:00
Noah Boorstin
21b1c4163c
busybear: add sim-busybear and sim-busybear-batch based on sim-wally
2021-03-01 21:01:15 +00:00
Noah Boorstin
62b441f3f5
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
4833b36535
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
Noah Boorstin
26d4024b33
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
Noah Boorstin
bcc0010498
Merge branch 'main' into busybear
2021-02-28 20:45:08 +00:00
Noah Boorstin
f306d2d2e1
busybear: start preloading bootmem
2021-02-28 20:43:57 +00:00
Noah Boorstin
db86d20d11
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
