Ross Thompson
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c749d08542
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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Katherine Parry
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efdec72df1
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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David Harris
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032c38b7e7
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MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
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2021-07-06 15:29:42 -04:00 |
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David Harris
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f805aea236
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Implemented TSR, TW, TVM, MXR status bits
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2021-07-06 01:32:05 -04:00 |
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David Harris
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8b23162d6d
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Fixed adrdecs to use Access signals for TIMs
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2021-07-05 23:42:58 -04:00 |
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David Harris
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6bac566bb7
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Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
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2021-07-05 20:35:31 -04:00 |
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bbracker
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39ae743543
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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Thomas Fleming
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5f2bccd88f
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Clean up PMA checker and begin PMP checker
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2021-04-29 02:20:39 -04:00 |
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Thomas Fleming
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4bae666fa1
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Implement virtual memory protection
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2021-04-21 19:58:36 -04:00 |
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Noah Boorstin
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f48af209c4
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busybear: make CSRs only weird for us
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2021-03-05 00:46:32 +00:00 |
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Noah Boorstin
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a03796a519
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busybear: change sstatus, mstatus reset value
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2021-02-28 16:19:03 +00:00 |
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kaveh pezeshki
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c7863d58cd
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merged with main to integrate with AHB
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2021-02-26 05:37:10 -08:00 |
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David Harris
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37dba8fd26
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More memory interface, ALU testgen
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2021-02-15 10:10:50 -05:00 |
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Noah Boorstin
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14cde0d59c
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Change CSR reset and available bits to conform to OVPsim
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
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2021-02-04 22:03:45 +00:00 |
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David Harris
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9d7e242596
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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396cea1ea7
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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