Ross Thompson
c31b7b4dc5
Wally previously was overcounting retired instructions when they were flushed.
...
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
c749d08542
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Ross Thompson
365485bd8b
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
David Harris
b5dddec858
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
David Harris
74b6d13195
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
336936cc39
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
bbracker
2bee4eabab
added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
2021-06-17 12:09:10 -04:00
bbracker
b65adbea63
enable TIME CSR for 32 bit mode as well
2021-06-17 11:34:16 -04:00
bbracker
5a661a7392
provide time and timeh CSRs based on CLINT's counter
2021-06-17 08:38:30 -04:00
David Harris
e41a87be23
Restored counter events
2021-06-10 11:18:58 -04:00
David Harris
3e8026dc21
Configurable number of performance counters
2021-06-10 09:41:26 -04:00
David Harris
01d6ca1e2a
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
Ross Thompson
6e803b724e
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Domenico Ottolia
0c307d2db1
Fix synthesis warnings for privileged unit (replace 'initial' settings)
2021-04-20 17:57:56 -04:00
Teo Ene
1018a10625
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Ross Thompson
9172e52286
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
a99c0502e5
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
Shreya Sanghai
1d6a2989ed
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Shreya Sanghai
08e9149e20
made performance counters count branch misprediction
2021-03-16 11:24:17 -04:00
Shreya Sanghai
246dbd05e7
fixed bugs
2021-03-04 12:59:45 -05:00
Shreya Sanghai
f0ec365117
added performance counters
2021-03-04 11:42:52 -05:00
David Harris
9d7e242596
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
