cturek
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d5c5450f8d
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Reoredered tests for arch32m
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2022-11-09 18:42:00 +00:00 |
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cturek
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333da5c945
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Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
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2022-11-06 22:08:18 +00:00 |
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David Harris
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c78643f4e4
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Reorder embench tests to prevent crash
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2022-11-04 15:21:51 -07:00 |
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Ross Thompson
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ae7a71c0f4
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Created one off test to replicate the floating point forwarding hazard bug.
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2022-10-22 16:29:12 -05:00 |
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Kip Macsai-Goren
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d5cd67cf09
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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David Harris
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fce927810a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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3b0714b059
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 10:35:11 -07:00 |
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David Harris
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1c8581dd6d
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Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
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2022-09-21 10:35:08 -07:00 |
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Ross Thompson
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91fcca9d17
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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David Harris
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8647de5ee4
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make QmM size b+1 indpenedent of radix
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2022-09-20 03:25:09 -07:00 |
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David Harris
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1e6bd26bb6
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Removed EarlyTermShift from fdiv
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2022-09-19 08:44:23 -07:00 |
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David Harris
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198a134304
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FP testbench
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2022-09-18 21:27:21 -07:00 |
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David Harris
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1187187a5c
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Divide testfloat starts with half-precision tests
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2022-09-18 06:46:47 -07:00 |
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Kip Macsai-Goren
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a4fc5d3476
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Created initial endianness tests
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2022-09-16 01:06:26 +00:00 |
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Ross Thompson
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40e7d2648f
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Renamed signals in the LSU.
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2022-09-13 11:47:39 -05:00 |
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David Harris
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c2f81e309b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-07 11:11:39 -07:00 |
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David Harris
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b0cf73d19c
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Running 16-bit square root cases first in testfloat
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2022-09-07 11:11:35 -07:00 |
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Ross Thompson
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fd4b382ec6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-07 12:26:50 -05:00 |
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David Harris
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e01b03e9b2
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Run 16-bit fsqrt tests first
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2022-09-07 10:26:09 -07:00 |
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Ross Thompson
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6581490f9c
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Modified regression tests to add some ahb configurations.
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2022-09-07 12:03:58 -05:00 |
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DTowersM
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dedfadbb14
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-31 00:18:04 +00:00 |
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DTowersM
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f9cbc9cf8e
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fixed qrduino keyerror in embench test
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2022-08-31 00:17:58 +00:00 |
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David Harris
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5956fbdd62
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Fixed checking termination in testfloat testbench
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2022-08-30 10:55:21 -07:00 |
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David Harris
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b4cb9a678a
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renamed srt to fdivsqrt
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2022-08-29 04:04:05 -07:00 |
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David Harris
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921a49921b
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Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
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2022-08-26 21:05:20 -07:00 |
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David Harris
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6409548c8b
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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906f6f2990
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Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
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Ross Thompson
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109bcd470e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 16:01:02 -05:00 |
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David Harris
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6222e15946
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Extended HADDR to PA_BITS
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2022-08-25 13:11:36 -07:00 |
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Ross Thompson
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32f86b1b6b
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Still not working with rv32ic.
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2022-08-25 15:03:54 -05:00 |
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Ross Thompson
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4ad7ccc7f7
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Possible fixes for earily messup of rv32ic and rv64ic configs.
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2022-08-25 14:42:08 -05:00 |
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Ross Thompson
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bd9401179d
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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5cc4f1f1cd
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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David Harris
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fe3147806d
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removed simpleram and modified dtim to use bram1p1rw
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2022-08-25 03:39:57 -07:00 |
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David Harris
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b3a13a01f8
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Stripped write capaibilty out of rom_ahb
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2022-08-24 17:23:08 -07:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c636387613
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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07b2858890
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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9e3d13ca52
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Q depends on D
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2022-08-23 08:29:59 -07:00 |
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David Harris
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7c91ed38a3
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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David Harris
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b795cf4731
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Updated testbench assertions.
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2022-08-23 07:23:24 -07:00 |
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Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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dad6770fc3
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Updated fpga testbench.
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2022-08-21 14:07:26 -05:00 |
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Katherine Parry
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0f077012c3
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sqrt tests in regression uncommented and pass
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2022-08-07 23:38:10 +00:00 |
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Katherine Parry
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8eeca3319c
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radix-2 1 copy passes testfloat
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2022-08-06 22:54:05 +00:00 |
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David Harris
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8b8f045491
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
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David Harris
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6ee8036ae7
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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David Harris
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e3b970d3ff
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Partitioned fma into separate files
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2022-08-01 18:07:38 +00:00 |
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David Harris
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da275e3c26
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Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
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