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9464c9022d
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38 Commits

Author SHA1 Message Date
Katherine Parry
9464c9022d floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
Shriya Nadgauda
c5a306426a finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
b7159652f6 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
968994c04a updated pipeline tests 2021-05-03 22:07:36 -04:00
Ross Thompson
818c0abc89 Fixed memory size in configs for rv32ic and rv64ic. 
Removed warning on call to $fscanf.
 2021-04-29 17:36:46 -05:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
bbracker
74b35ac57a greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Noah Boorstin
6954e6df4c buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
bbracker
290b3424e5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
92bb38fa8c Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Shreya Sanghai
0369fc5d1e Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
bbracker
11d4a8ab34 first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Noah Boorstin
bc1a0c6ee7 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
a2b0af460e everyone gets a bootram 2021-03-18 12:35:37 -04:00
Shreya Sanghai
36f0631203 added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Shreya Sanghai
74f1641c5a Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Ross Thompson
4c8952de6a Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Thomas Fleming
1294235837 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
17c0f9629a WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
8c97143be6 Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Shreya Sanghai
f0ec365117 added performance counters 2021-03-04 11:42:52 -05:00
David Harris
d00d42cf9a Merged bus into main 2021-02-25 00:28:41 -05:00
David Harris
8dec69c2ce Added MUL 2021-02-15 22:27:35 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
David Harris
a357f2a0e7 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
9a51bb27c3 Implemented adrdec for uncore 2021-01-29 17:28:53 -05:00
David Harris
ed3cb83c10 Added ahblite bus interface unit 2021-01-29 01:07:17 -05:00
David Harris
b88508ca11 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
David Harris
1d9c741c00 Reset Vector moved to config file 2021-01-25 15:57:36 -05:00
David Harris
fa18052348 Added test configurations 2021-01-25 11:28:43 -05:00