Ross Thompson
92fc532b82
Created scripts to install imperas and run a single test using imperas.
2023-01-31 13:51:05 -06:00
Ross Thompson
d821105697
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-01-31 13:04:41 -06:00
Ross Thompson
c9c4f63c18
Fixed remaining bugs in the imperas merge.
2023-01-31 13:04:26 -06:00
Ross Thompson
026071e247
Merge branch 'imperas'
2023-01-31 12:46:22 -06:00
Ross Thompson
5a770f148c
Minor bug fix in gshare.
2023-01-31 10:45:32 -06:00
Ross Thompson
ad0a0f0d51
Renamed signals in RAS.
2023-01-31 10:44:11 -06:00
Ross Thompson
0e3c77bed3
Found small bug in gshare.
2023-01-31 00:17:49 -06:00
Ross Thompson
939095615f
Fixed parameterization in testbench.
2023-01-31 00:11:01 -06:00
Ross Thompson
8feac6d242
Parameterized testbench branch predictor preload.
2023-01-31 00:08:11 -06:00
Ross Thompson
238c4d14a9
More branch predictor cleanup.
2023-01-30 23:55:52 -06:00
Ross Thompson
80f50f10d3
Improved signal names.
2023-01-30 23:51:04 -06:00
Ross Thompson
a15889e0aa
Major cleanup of branch predictor.
2023-01-30 23:37:34 -06:00
Ross Thompson
42828e6ec4
Simplified gshare.
2023-01-30 19:27:18 -06:00
Ross Thompson
4cbefd9834
Minor gshare optimization.
2023-01-30 18:13:12 -06:00
Madeleine Masser-Frye
5625996f44
Merged conflicts in fixing synthesis config/hdl writing ( #40 )
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* Fixed writing config files for synth sweeps
* cleaned up comments
* Fixed copying hdl subdirectories and referencing the correct config files for modified features
* improved readability for synth scripts
* cleans run directory post run and leaves copy of wally-config
2023-01-30 20:54:19 +02:00
David Harris
d38f4a040c
Merge pull request #38 from ross144/main
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Imperas found bug with hptw
2023-01-30 10:10:41 -08:00
Ross Thompson
cc48cdc97b
Imperas found a real bug in virtual memory.
...
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.
Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
2023-01-30 11:47:51 -06:00
Ross Thompson
f667843ce9
Merge branch 'main' of github.com:ross144/cvw
2023-01-29 22:39:53 -06:00
Ross Thompson
6040a45698
optimized branch predictor by removing unnecessary registers.
2023-01-29 22:39:37 -06:00
Ross Thompson
50ea630d31
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-01-29 22:19:10 -06:00
Ross Thompson
392716a608
Updated global history branch predictcor with the gshare improvements.
2023-01-29 16:26:44 -06:00
David Harris
d7c5f4089f
Merge pull request #37 from ross144/main
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Major update to branch predictor
2023-01-29 14:18:31 -08:00
Ross Thompson
a9a7054e2f
Merge branch 'main' of https://github.com/openhwgroup/cvw
...
This merges the branch predictor improvements into the main repo.
2023-01-29 15:24:20 -06:00
Ross Thompson
d6ae1156d0
gshare cleanup.
2023-01-29 15:07:45 -06:00
Ross Thompson
ef874f3409
Gshare cleanup.
2023-01-29 15:06:35 -06:00
Ross Thompson
74b4f78099
Found bug in gshare.
2023-01-29 15:03:25 -06:00
Ross Thompson
1a418d9fe2
Updated benchmark parsing script.
2023-01-29 14:17:45 -06:00
David Harris
5c83c6fb02
Merge pull request #34 from stineje/main
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Update Appendix D + wrapped memories
2023-01-29 07:10:35 -08:00
Ross Thompson
e1fd5925b0
Fixed typo in testbench branch logger.
2023-01-29 01:00:52 -06:00
Ross Thompson
f62fbedbe8
Fixed another bug with the branch logger.
2023-01-29 00:59:59 -06:00
Ross Thompson
8e73f6b467
Fixed bug in the branch logger.
2023-01-29 00:58:50 -06:00
Ross Thompson
65a31381da
Updated testbench for branch logger.
2023-01-29 00:56:11 -06:00
Ross Thompson
1044c290c2
Fixed bug with the btb's valid bit not beind held on a stall.
2023-01-29 00:49:23 -06:00
Ross Thompson
f93eaeef8e
Fixed another bug with the speculative gshare with instruction class prediction.
2023-01-29 00:33:40 -06:00
James E. Stine
c05ccc88d4
Merge pull request #33 from davidharrishmc/dev
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Dev
2023-01-28 23:22:27 -06:00
David Harris
99d12a5ef0
Removed unused BPRED file referenes from fpga config
2023-01-28 20:22:36 -08:00
David Harris
481cb8bad0
Renamed BPTYPE to BPRED_TYPE
2023-01-28 20:06:12 -08:00
David Harris
94daedeed6
Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED
2023-01-28 18:52:00 -08:00
David Harris
e4e7e827d6
Renamed BUS to BUS_SUPPORTED
2023-01-28 18:35:53 -08:00
David Harris
8b34f5ac98
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-28 18:18:53 -08:00
David Harris
5a8cbc65a7
Merge pull request #35 from kipmacsaigoren/main
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Updated test library to fix test dependence on BP status
2023-01-28 18:18:34 -08:00
David Harris
a0b4e7fb24
Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED
2023-01-28 18:17:42 -08:00
David Harris
33143e5958
Fixed typo in ram2p1r1wbe_1024x69 and renamed for consistency
2023-01-28 18:07:33 -08:00
David Harris
1bb1fc7604
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-28 17:55:08 -08:00
James Stine
704542d813
Update Appendix D + wrapped memories
2023-01-28 19:46:43 -06:00
James Stine
a1d892703c
Modified changes as follows
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* Add docs directory for Docker including Dockerfile
* Change to synthesis script to include fpu stuff
* Add wrappers for IP (may need some cleanup but will cleanup shortly)
2023-01-28 19:33:00 -06:00
Kip Macsai-Goren
95b26c49b9
Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
2023-01-28 17:29:35 -08:00
Ross Thompson
f6aafd6bad
Fixed bug with the new csr.
2023-01-28 17:56:56 -06:00
Ross Thompson
6371d91b37
Added another performance counter to track overall branch miss-predictions.
2023-01-28 17:50:46 -06:00
Ross Thompson
57deb68fb3
Found an issue where the btb was not forwarding the valid bit!
2023-01-28 17:00:50 -06:00
