Kip Macsai-Goren
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324d3fcea5
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added working general trap tests to regression
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2022-04-20 06:48:01 +00:00 |
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Kip Macsai-Goren
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121cc627f6
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Added working trap test to regression, fixed hanfling of some interrupts
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2022-04-18 07:22:16 +00:00 |
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Ross Thompson
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61dbf13a69
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Fixed bug I introduced by csrc cleanup and changes to ILA.
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2022-04-17 21:45:46 -05:00 |
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David Harris
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5bb521635e
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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Kip Macsai-Goren
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331efcedc4
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added new tests to makefrag and tests.vh
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2022-04-17 21:00:36 +00:00 |
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David Harris
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c3bca40e05
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Added WFI to the testbench instruction name decoder
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2022-04-14 17:12:11 +00:00 |
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bbracker
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0e183be3e5
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fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
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2022-04-14 09:23:21 -07:00 |
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bbracker
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489ce4269a
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fix ReadDataM forcing
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2022-04-13 15:32:00 -07:00 |
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Ross Thompson
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65573f07b7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-13 13:39:47 -05:00 |
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bbracker
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016e960401
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change interrupt spoofing to happen at negative clock edges
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2022-04-13 04:31:23 -07:00 |
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bbracker
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3465d8cd32
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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67ef47b25b
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whoops forgot to update AttemptedInstructionCount in interrupt spoofing
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2022-04-13 00:49:37 -07:00 |
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bbracker
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6c3d274970
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change testbench-linux to by default use attempted instruction count for warning/error messages
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2022-04-12 21:22:08 -07:00 |
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Ross Thompson
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adb4e30c45
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Missed the force on uart for no tracking.
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2022-04-12 19:37:44 -05:00 |
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Ross Thompson
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56bea58a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-10 13:41:27 -05:00 |
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Ross Thompson
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fc5eac6820
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Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
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2022-04-10 13:27:54 -05:00 |
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bbracker
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c0c5733a1d
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upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
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2022-04-08 13:45:27 -07:00 |
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bbracker
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23406d0926
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small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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Ross Thompson
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1614996941
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Fixed typo in tests.vh
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2022-04-07 16:28:28 -05:00 |
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Kip Macsai-Goren
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c3a6b88acc
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updated test signature locations
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2022-04-06 07:28:38 +00:00 |
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Katherine Parry
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c3d07b2c46
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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51dfa16f59
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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e4f4e1bd43
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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839bede656
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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997c1b87fe
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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66e9380cfb
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Kip Macsai-Goren
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d031c003ba
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fixed arch bge test signature output location after update
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2022-03-29 20:45:18 +00:00 |
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Kip Macsai-Goren
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a6d90a25c2
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fixed signature location of the new periph with no compressed instructions
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2022-03-29 02:15:17 +00:00 |
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Skylar Litz
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f91fb7a388
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add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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Kip Macsai-Goren
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7ae1d14191
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added basic trap tests that do not pass regression yet. updated signature adresses
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2022-03-25 22:57:41 +00:00 |
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bbracker
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6f6663cd67
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fix multiple-context PLIC checkpoint generation
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2022-03-25 01:02:22 +00:00 |
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bbracker
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d33de3ef6b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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bbracker
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4b376e2834
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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71aad2d213
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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aa60b57fb3
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Cleanup in testbench-linux.sv.
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2022-03-22 22:34:38 -05:00 |
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Ross Thompson
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b2487f4b72
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-22 21:28:50 -05:00 |
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Ross Thompson
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4ca9458534
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added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
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2022-03-22 21:28:34 -05:00 |
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Ross Thompson
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e6b42cb10f
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Added spoof of uart addresses +0x2 and +0x6.
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2022-03-22 16:52:27 -05:00 |
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Katherine Parry
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e3d01c875b
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FMA parameterized and FMA testbench reworked
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2022-03-19 19:39:03 +00:00 |
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Ross Thompson
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7a25d577ba
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Added new asserts to testbench.
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2022-03-11 15:41:53 -06:00 |
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bbracker
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742e8d98cd
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fix up PLIC and UART checkpointing
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2022-03-07 23:48:47 -08:00 |
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bbracker
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92e1583db5
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change testbench-linux.sv to use new shared location of disassembly files
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2022-03-07 20:04:08 -08:00 |
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David Harris
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e4d18f1808
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removed more old 64priv tests
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2022-03-04 03:57:19 +00:00 |
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bbracker
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c3e59ae2df
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comment out nonfunctioning CSR-PERMISSIONS-M test
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2022-03-04 00:11:55 +00:00 |
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bbracker
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79ff8d3c80
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remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
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bbracker
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87aad1d953
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fix peripheral test and add it to regression
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2022-03-02 23:44:39 +00:00 |
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bbracker
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4fe35aadf2
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add rv32a tests to regression
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2022-03-02 17:54:55 +00:00 |
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bbracker
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b6031bb15f
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fix buildroot checkpointing and add it back to regression
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2022-03-02 16:00:19 +00:00 |
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bbracker
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29179c6787
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add LRSC test and add wally64a to regression
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2022-03-02 07:09:37 +00:00 |
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