Ross Thompson
730fdb029a
Fixed bug with DAPageFault being wrong when HPTW writes not supported.
2022-02-23 10:54:34 -06:00
Ross Thompson
6f53f7943f
More spillsupport more structual.
2022-02-23 10:27:14 -06:00
Ross Thompson
19ec874641
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
15f6871a8d
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
834b308ed6
Fixed "bug" with wally-pipelined.do
2022-02-22 22:19:25 -06:00
Ross Thompson
59f04f2518
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
ea29291024
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-22 14:45:53 -06:00
Ross Thompson
971dd494f6
Clarified interlockfsm.
2022-02-22 11:31:28 -06:00
bbracker
2322e66f9f
fix lint bugs in PLIC and UART
2022-02-22 05:04:18 +00:00
bbracker
ac114e1c6d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-22 04:27:50 +00:00
bbracker
202bd2f8f8
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
bbracker
c26526c9f3
change RX side of UART to aslo be LSB-first
2022-02-22 03:34:08 +00:00
Ross Thompson
1ab2e7590b
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
8a280f211f
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
3ba70b74d6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 12:46:22 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
ushakya22
5f916d17d2
Moved order of reading a, b, and result from test vectors file so that result
...
matches up with inputs a and b
2022-02-21 17:28:11 +00:00
ushakya22
3abc2c0592
- created new testbench file instead of having it at the bottom of the srt file
...
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench
Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
2022-02-21 16:24:50 +00:00
ushakya22
1ea3e8120a
- Created exponent divsion module
...
- top module includes exponent module now
Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
2022-02-21 16:13:30 +00:00
ushakya22
3d5b407755
Changed Makefile to compile exptestgen instead of testgen
2022-02-21 16:08:45 +00:00
ushakya22
ec3fa45f86
reverted srt_standford back to original file pre modifications by Udeema
2022-02-21 16:08:09 +00:00
ushakya22
ed452aff5f
verilator lint for srt
2022-02-21 16:05:43 +00:00
ushakya22
a3a572fe5f
Created test vector generation file for exponent and mantissa division
2022-02-21 16:04:41 +00:00
Ross Thompson
5d9ad011d2
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
8af055c78e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 09:06:09 -06:00
Kip Macsai-Goren
04892c5d38
added scratch register tests for 64 and 32 bits
2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
d852e8a5c1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-21 00:34:54 +00:00
Ross Thompson
a60332b455
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
David Harris
4e194b2576
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Kip Macsai-Goren
324efa7d42
added 32 bit pma tests to regression even though they've been working fo a while
2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
dcb5d0f6a9
Added misa test for both 32 and 64 bits
2022-02-18 19:41:50 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
David Harris
3036de316a
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
460b37b21a
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Ross Thompson
beac362364
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
84edb8b5d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
bd7343b791
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
David Harris
131a1a4ded
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
799736632b
Register file comments about reset
2022-02-16 17:21:05 +00:00
Ross Thompson
a64839d999
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
Skylar Litz
03f23d2aaa
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
