slmnemo
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e4f0f55530
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Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.
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2022-05-17 01:04:13 +00:00 |
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slmnemo
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7656e3031c
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quit
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2022-05-17 01:03:09 +00:00 |
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David Harris
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14f9f41d2d
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Partitioned privileged pipeline registers into module
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2022-05-12 20:45:45 +00:00 |
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David Harris
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39ceb3a550
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Partitioned privilege mode fsm into new module
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2022-05-12 16:16:42 +00:00 |
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David Harris
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1aa3e65bae
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Removed more unused signals, simplified csri state
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2022-05-12 15:10:10 +00:00 |
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mmasserfrye
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6cba6a92ba
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filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv
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2022-05-12 07:22:06 +00:00 |
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David Harris
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8166fd772e
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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137b411bea
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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7f42ff06d2
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SFENCE.VMA should be illegal in user mode
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2022-05-05 15:15:02 +00:00 |
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David Harris
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9b7aab122e
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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David Harris
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1a7599ce94
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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895a4f4832
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updated makefrag and tests.vh to reflect removed tests, new names
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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75e90f193e
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added missing SIE test
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2022-04-29 19:54:29 +00:00 |
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Kip Macsai-Goren
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c0b56bfd27
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renamed PIE-stack tests to status-mie for clarity
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2022-04-29 18:30:39 +00:00 |
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Kip Macsai-Goren
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c47ec36bc7
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removed old unused tests from wally arch tests
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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aedf0341af
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added 32 bit versions of new tests. all but timeout wait pass regression
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2022-04-28 18:14:07 +00:00 |
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Skylar Litz
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64a537c59b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-27 10:50:19 -07:00 |
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Skylar Litz
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f2b6842edb
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fix AttemptedInstructionCount from ground zero
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2022-04-27 10:45:40 -07:00 |
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Kip Macsai-Goren
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74b103fae4
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added working tests to test list, updated regression for new configs
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2022-04-25 19:18:15 +00:00 |
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Kip Macsai-Goren
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01f8bdfafc
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added new tests to tests.vh, comented out until they pass regression
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2022-04-25 18:22:44 +00:00 |
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David Harris
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1a8369b02b
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Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
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2022-04-25 14:49:00 +00:00 |
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Ross Thompson
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e56b9f18d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-21 09:52:42 -05:00 |
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Kip Macsai-Goren
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25d0f6305a
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added new tests to tests.vh
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2022-04-20 17:34:40 +00:00 |
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Kip Macsai-Goren
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324d3fcea5
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added working general trap tests to regression
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2022-04-20 06:48:01 +00:00 |
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Ross Thompson
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b94927d8a6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-19 14:09:50 -05:00 |
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Kip Macsai-Goren
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121cc627f6
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Added working trap test to regression, fixed hanfling of some interrupts
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2022-04-18 07:22:16 +00:00 |
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Ross Thompson
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61dbf13a69
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Fixed bug I introduced by csrc cleanup and changes to ILA.
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2022-04-17 21:45:46 -05:00 |
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Ross Thompson
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3add26be64
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fixed no forcing bug in linux testbench.
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2022-04-17 17:49:51 -05:00 |
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David Harris
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5bb521635e
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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Kip Macsai-Goren
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331efcedc4
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added new tests to makefrag and tests.vh
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2022-04-17 21:00:36 +00:00 |
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David Harris
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c3bca40e05
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Added WFI to the testbench instruction name decoder
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2022-04-14 17:12:11 +00:00 |
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bbracker
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0e183be3e5
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fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
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2022-04-14 09:23:21 -07:00 |
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bbracker
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489ce4269a
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fix ReadDataM forcing
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2022-04-13 15:32:00 -07:00 |
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Ross Thompson
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65573f07b7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-13 13:39:47 -05:00 |
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bbracker
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016e960401
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change interrupt spoofing to happen at negative clock edges
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2022-04-13 04:31:23 -07:00 |
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bbracker
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3465d8cd32
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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67ef47b25b
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whoops forgot to update AttemptedInstructionCount in interrupt spoofing
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2022-04-13 00:49:37 -07:00 |
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bbracker
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6c3d274970
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change testbench-linux to by default use attempted instruction count for warning/error messages
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2022-04-12 21:22:08 -07:00 |
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Ross Thompson
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adb4e30c45
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Missed the force on uart for no tracking.
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2022-04-12 19:37:44 -05:00 |
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Ross Thompson
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56bea58a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-10 13:41:27 -05:00 |
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Ross Thompson
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fc5eac6820
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Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
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2022-04-10 13:27:54 -05:00 |
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bbracker
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c0c5733a1d
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upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
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2022-04-08 13:45:27 -07:00 |
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bbracker
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23406d0926
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small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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Ross Thompson
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1614996941
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Fixed typo in tests.vh
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2022-04-07 16:28:28 -05:00 |
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Kip Macsai-Goren
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c3a6b88acc
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updated test signature locations
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2022-04-06 07:28:38 +00:00 |
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Katherine Parry
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c3d07b2c46
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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51dfa16f59
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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e4f4e1bd43
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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839bede656
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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