Commit Graph

17 Commits

Author SHA1 Message Date
bbracker
23f479d225 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR 2021-06-20 22:38:25 -04:00
David Harris
35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
679e507cc6 Added SUPPORTED to each peripheral in each config file 2021-06-17 21:36:32 -04:00
David Harris
3e8026dc21 Configurable number of performance counters 2021-06-10 09:41:26 -04:00
David Harris
0ffbd03139 More verilator fixes, but bpred is broken 2021-06-09 21:03:03 -04:00
Kip Macsai-Goren
a95a7a7b82 working version with new mmu comments, old boottim values 2021-06-08 15:20:25 -04:00
David Harris
b613f46c2d Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
David Harris
2ae5ca19b5 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
dc0b19dfaa Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4 Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
David Harris
a26bf37be8 Started MMU 2021-06-04 11:59:14 -04:00
James E. Stine
44dc665fc5 Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) 2021-05-18 13:48:44 -05:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Noah Boorstin
6954e6df4c buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Shreya Sanghai
7e9a0602ea fixed bugs in global history to read latest GHRE
Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00