David Harris
24a05c35d9
Renamed signals for LSU - FPU interface
2022-08-22 13:47:56 -07:00
David Harris
7151befd04
Removed FStore2 and simplified HPTW
2022-08-22 13:29:54 -07:00
Ross Thompson
a049f456e8
Removed logic from Verilog wrapper.
2022-08-21 14:07:43 -05:00
Ross Thompson
5d9dab6149
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
Katherine Parry
2ada8a8bc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-07-12 22:37:20 +00:00
Katherine Parry
ca4fe08fd9
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
David Harris
381f3298d8
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
2022-07-08 09:09:02 +00:00
David Harris
2f342c430e
fixing port errors
2022-07-07 21:57:10 +00:00
David Harris
d73645944f
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
Katherine Parry
6baded9121
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
Katherine Parry
254ebf478e
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
Katherine Parry
31fd8772cf
postprocessing unit created and passing all tests
2022-06-13 22:47:51 +00:00
slmnemo
054cf5f7b0
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
284e0395a0
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
73e0c1c07f
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
1d8bc2dc1b
Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
2022-06-02 09:37:59 -07:00
David Harris
c7ec9282fe
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
847c7930c4
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
08430a1e85
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
ce24c080d5
More unused signal cleanup
2022-05-12 15:26:08 +00:00
David Harris
5670f77de2
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
e2e63ca9a8
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
8166fd772e
Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
2022-05-11 15:08:33 +00:00
David Harris
137b411bea
Removed M suffix from interrupts because they are generated asynchronously to pipeline
2022-05-11 14:41:55 +00:00
David Harris
4f1b0fdc64
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
David Harris
a516f89f22
WFI terminates when an interrupt is pending even if interrupts are globally disabled
2022-05-08 04:30:46 +00:00
David Harris
412d4656ed
Zero'd wfiM when ZICSR not supported to fix hang in E tests
2022-05-05 15:32:13 +00:00
David Harris
1a7599ce94
Changed WFI to stall pipeline in memory stage
2022-05-05 02:03:44 +00:00
David Harris
1166c40059
FPU generates illegal instruction if MSTATUS.FS = 00
2022-05-03 11:56:31 +00:00
Kip Macsai-Goren
bd87af478a
Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
2022-04-22 22:46:11 +00:00
Ross Thompson
2376d66ec2
Added more ILA signals.
2022-04-02 16:39:45 -05:00
bbracker
69a0f6e00b
big interrupts refactor
2022-03-30 13:22:41 -07:00
bbracker
8ea25e591b
fix typo that Madeleine found
2022-03-28 15:39:29 -07:00
bbracker
d33de3ef6b
tabs vs spaces disagreement
2022-03-24 17:11:41 -07:00
bbracker
4b376e2834
1st attempt at multiple channel PLIC
2022-03-24 17:08:10 -07:00
Ross Thompson
71aad2d213
Moved WriteDataM register into LSU.
2022-03-23 14:17:59 -05:00
Ross Thompson
654c4d1148
simplified uncore's name for HWDATA.
2022-03-10 18:17:44 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
e06fb923a1
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
459f4bd3b4
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
2a64b1bc95
Used .* in wrapper
2022-01-07 05:23:42 +00:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
e5f9fbb238
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
