David Harris
8a43d6099b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-05-03 18:32:04 +00:00
David Harris
4b91fddc0a
Illegal instruction fault when running FPU instruction with STATUS_FS = 0
2022-05-03 18:32:01 +00:00
David Harris
3efbd2565a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-05-03 08:53:35 -07:00
David Harris
20bbe43a23
clean up sram1p1rw; still doesn't work on Modelsim 2022.1
2022-05-03 08:31:54 -07:00
David Harris
1166c40059
FPU generates illegal instruction if MSTATUS.FS = 00
2022-05-03 11:56:31 +00:00
David Harris
bcd8728b3e
Switched to behavioral comparator for best PPA
2022-05-03 11:00:39 +00:00
David Harris
b4a422f771
Comparator experiments
2022-05-03 10:54:30 +00:00
David Harris
057524b840
Formatting cache.sv
2022-05-03 10:53:20 +00:00
David Harris
9e50c3440d
sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera
2022-05-03 03:50:41 -07:00
David Harris
0df73d203b
Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
2022-05-03 03:45:41 -07:00
David Harris
9e47fca2b7
Changed loop variable in CLINT because of error only seen on VLSI
2022-05-03 10:10:28 +00:00
David Harris
515270a8cf
Added torture.tv test vectors
2022-04-27 13:08:36 +00:00
David Harris
cce0a421be
Checked in torture.tv
2022-04-27 13:06:24 +00:00
David Harris
9d82232c14
Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv
2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
33875b20b5
fixed initial value, timing on fs bits changing after floating point instruction
2022-04-25 19:17:29 +00:00
David Harris
0957b7040d
Restored MPRV behavior per spec
2022-04-25 14:52:18 +00:00
David Harris
1a8369b02b
Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
2022-04-25 14:49:00 +00:00
David Harris
142636173e
Added MTINST hardwired to 0, and added timeout of U-mode WFI
2022-04-24 20:00:02 +00:00
David Harris
28e8aa4f97
Fixed InstrMisalignedFaultM mtval
2022-04-24 17:31:30 +00:00
David Harris
ffecdda6e6
Improved priority order and mtval of traps to match spec
2022-04-24 17:24:45 +00:00
David Harris
04b0579b89
Extended sim time to fully boot Linux. Added comments to hazard unit
2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
bd87af478a
Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
2022-04-22 22:46:11 +00:00
bbracker
9c1e398bb5
change how tristate I/O is spoofed in GPIO loopback test
2022-04-21 10:31:16 -07:00
David Harris
1e19cf9f14
Simplified profile for UART boot; added warnings on UART Rx errors
2022-04-21 04:54:45 +00:00
David Harris
c57b9e6703
Added baby torture tests
2022-04-19 15:13:06 +00:00
David Harris
eaa0d44980
Fixed WFI decoding in IFU
2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
ced763beb6
Added GPIO loopback to let outputs cause interrupts
2022-04-18 07:22:49 +00:00
Shreya Sanghai
6f0085201b
replaced k with bpred size
2022-04-18 04:21:03 +00:00
David Harris
22842816a8
LSU name cleanup
2022-04-18 03:18:38 +00:00
David Harris
e04febdb57
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-04-18 01:30:11 +00:00
David Harris
c07b9d1722
Renamed FinalAMOWriteDataM to AMOWriteDataM
2022-04-18 01:30:03 +00:00
Ross Thompson
a5d4e39e7d
Added back the instret counter to ILA.
2022-04-17 18:44:07 -05:00
David Harris
d8b4c985cd
Remvoed bytemask anding from FinalWriteDataM in subwordwrite
2022-04-17 22:33:25 +00:00
David Harris
6bb4cd1bca
Prefix comparator cleanup
2022-04-17 21:53:11 +00:00
David Harris
5bb521635e
Experiments with prefix comparator; minor fixes in WFI and testbench warnings
2022-04-17 21:43:12 +00:00
Ross Thompson
5a6ad32688
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-17 15:23:46 -05:00
Ross Thompson
7135364d1a
Increased uart baud rate to 230400.
...
Added uart signals to debugger.
2022-04-17 15:23:39 -05:00
David Harris
b4902a6ff9
First implementation of WFI timeout wait
2022-04-17 17:20:35 +00:00
David Harris
6769f0cb43
Added comments in fcvt
2022-04-17 16:53:10 +00:00
David Harris
d71940d96d
Simplified SLT logic
2022-04-17 16:49:51 +00:00
Ross Thompson
f8bdb6db49
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-16 14:59:03 -05:00
Ross Thompson
bfc68bef69
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
David Harris
0932d4df46
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
David Harris
6e16922aae
WFI should set EPC to PC+4
2022-04-14 17:05:22 +00:00
Ross Thompson
22f2e88553
UART and clock speed changes to support 30Mhz.
2022-04-12 17:56:36 -05:00
Ross Thompson
396f697d2f
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
de868ef3a2
Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
2022-04-07 16:56:28 -05:00
Katherine Parry
74e0db04ac
fixed errors and warnings in rv32e
2022-04-07 17:21:20 +00:00
Ross Thompson
900939581e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-05 15:42:07 -05:00
