16 Commits

Author	SHA1	Message	Date
David Harris	861ef5e1cb	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
David Harris	38772de21f	Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram	2021-07-08 16:58:11 -04:00
David Harris	1190729896	TLB cleanup to match diagrams	2021-07-08 16:52:06 -04:00
David Harris	2bab3f769b	Renamed tlb ReadLines to Matches	2021-07-07 06:32:26 -04:00
David Harris	7d857cf4bd	more TLB name touchups	2021-07-06 18:39:30 -04:00
David Harris	d58cad89a8	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
David Harris	b0f199b574	Fixed TLB_ENTRIES merge conflict and handling of global PTEs	2021-07-04 18:05:22 -04:00
David Harris	80666f0a71	Added ASID & Global PTE handling to TLB CAM	2021-07-04 17:52:00 -04:00
David Harris	07ef67e537	Restructured TLB Read as AND-OR operation with one-hot match/read line	2021-07-04 17:01:22 -04:00
David Harris	8337d6df68	Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders	2021-07-04 16:33:13 -04:00
David Harris	c281539f36	TLB cleanup	2021-07-04 14:59:04 -04:00
David Harris	735f3b4217	Replaced generates with arrays in TLB	2021-07-04 12:32:27 -04:00
David Harris	1ec90a5e1f	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
Kip Macsai-Goren	d6f47d5917	making mmu branch line up with main	2021-06-08 13:59:03 -04:00
Kip Macsai-Goren	49515245d9	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
Kip Macsai-Goren	1e174a8244	got rid of some underscores in filenames, modules	2021-06-07 18:54:05 -04:00