David Harris
6769f0cb43
Added comments in fcvt
2022-04-17 16:53:10 +00:00
David Harris
d71940d96d
Simplified SLT logic
2022-04-17 16:49:51 +00:00
Ross Thompson
55c667b60d
Commented output power analysis to speed simulation.
2022-04-16 15:32:59 -05:00
Ross Thompson
b3153bc71e
Updated wally to point to riscv-arch-test tag 2.7.3
2022-04-16 15:32:43 -05:00
Ross Thompson
881695582b
commented out wally-scratch test as it hangs during compile.
2022-04-16 15:09:17 -05:00
Ross Thompson
f8bdb6db49
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-16 14:59:03 -05:00
Ross Thompson
bfc68bef69
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
James E. Stine
be917cdee6
Update mkdir in run_all.sh to guarantee no errors
2022-04-14 22:23:23 -05:00
David Harris
0932d4df46
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
David Harris
c3bca40e05
Added WFI to the testbench instruction name decoder
2022-04-14 17:12:11 +00:00
David Harris
6e16922aae
WFI should set EPC to PC+4
2022-04-14 17:05:22 +00:00
bbracker
0e183be3e5
fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
2022-04-14 09:23:21 -07:00
bbracker
489ce4269a
fix ReadDataM forcing
2022-04-13 15:32:00 -07:00
bbracker
20c82b6f1a
parsePlicState.py bugfix
2022-04-13 13:04:43 -07:00
Ross Thompson
65573f07b7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-13 13:39:47 -05:00
bbracker
c697c17b05
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-13 05:35:56 -07:00
bbracker
016e960401
change interrupt spoofing to happen at negative clock edges
2022-04-13 04:31:23 -07:00
bbracker
3465d8cd32
improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
2022-04-13 03:37:53 -07:00
bbracker
0d4ec9b3f9
fix bugs in PLIC checkpoint state parsing
2022-04-13 01:59:21 -07:00
bbracker
1bb5e1f35b
whoops fix address for PLIC int enables in checkpoint generation
2022-04-13 01:36:09 -07:00
bbracker
67ef47b25b
whoops forgot to update AttemptedInstructionCount in interrupt spoofing
2022-04-13 00:49:37 -07:00
bbracker
6c3d274970
change testbench-linux to by default use attempted instruction count for warning/error messages
2022-04-12 21:22:08 -07:00
Ross Thompson
2eb2263e94
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-12 19:38:04 -05:00
Ross Thompson
adb4e30c45
Missed the force on uart for no tracking.
2022-04-12 19:37:44 -05:00
Ross Thompson
d087deef65
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-12 17:56:48 -05:00
Ross Thompson
22f2e88553
UART and clock speed changes to support 30Mhz.
2022-04-12 17:56:36 -05:00
Ross Thompson
396f697d2f
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
56bea58a3c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-10 13:41:27 -05:00
Ross Thompson
fc5eac6820
Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
2022-04-10 13:27:54 -05:00
bbracker
c0c5733a1d
upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
2022-04-08 13:45:27 -07:00
bbracker
23406d0926
small signs of life on new interrupt spoofing
2022-04-08 12:32:30 -07:00
bbracker
a09360f207
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 19:43:27 -07:00
bbracker
54c5f7f607
deprecate remove_dup.awk in favor of expanding parseGDBtoTrace.py to internally remove duplicates; this way the instruction counts in traps.txt are hopefully now in sync with the line numbers of all.txt
2022-04-07 19:43:22 -07:00
Ross Thompson
9685365d2e
Added signals to ila.
2022-04-07 21:09:50 -05:00
Ross Thompson
6702e2c735
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 16:56:56 -05:00
Ross Thompson
de868ef3a2
Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
2022-04-07 16:56:28 -05:00
Ross Thompson
22279a29ab
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 16:29:48 -05:00
Ross Thompson
54de15752e
Added sp to ila.
2022-04-07 16:29:41 -05:00
Ross Thompson
1614996941
Fixed typo in tests.vh
2022-04-07 16:28:28 -05:00
Katherine Parry
3224512812
re-adding an empty 'vectors' folder
2022-04-07 17:44:08 +00:00
Katherine Parry
72e4ab8361
cleaned floating point 'vectors' folder
2022-04-07 17:31:08 +00:00
Katherine Parry
74e0db04ac
fixed errors and warnings in rv32e
2022-04-07 17:21:20 +00:00
bbracker
008089b470
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-07 08:37:44 -07:00
bbracker
0a0956fad0
fix parseQEMUtoGDB.py to pass on interrupt messages correctly
2022-04-07 04:47:15 -07:00
kaveh Pezeshki
49aae4b2e9
using -S for busybox objdump to provide source code snippets
2022-04-06 23:06:49 +00:00
bbracker
0f394ba18b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-06 07:50:57 -07:00
bbracker
0a8ce0593a
filter traps list down to just interrupts
2022-04-06 07:49:44 -07:00
bbracker
ea0471dcc7
change RAM size in genInitMem.sh
2022-04-06 07:49:04 -07:00
Kip Macsai-Goren
c3a6b88acc
updated test signature locations
2022-04-06 07:28:38 +00:00
