56 Commits

Author	SHA1	Message	Date
Katherine Parry	254ebf478e	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
slmnemo	3fe78c9084	Fixed recurrent issue with testbench where it would never stop	2022-06-03 18:56:24 -07:00
slmnemo	88454aa2ab	Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do" ... This reverts commit 89c7438424.	2022-06-02 12:45:21 -07:00
slmnemo	ad9e85beb9	Revert "Fixed buildroot by adding a second ." ... This reverts commit 8b27c1884e.	2022-06-02 12:43:59 -07:00
slmnemo	65961223f8	Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files	2022-06-02 02:51:51 +00:00
slmnemo	f18989e801	Revert Commit 6c61840045	2022-05-28 03:35:17 -07:00
slmnemo	6c61840045	Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do	2022-05-28 03:14:49 -07:00
slmnemo	e3a7e3e2f3	changes suggested by ben, hopefully fixing buildroot (which is now not running)	2022-05-20 18:42:38 -07:00
slmnemo	8b27c1884e	Fixed buildroot by adding a second .	2022-05-19 17:49:32 -07:00
slmnemo	89c7438424	parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do	2022-05-19 16:21:38 -07:00
David Harris	39ceb3a550	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	1aa3e65bae	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	8166fd772e	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	137b411bea	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
Skylar Litz	64a537c59b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-27 10:50:19 -07:00
Skylar Litz	f2b6842edb	fix AttemptedInstructionCount from ground zero	2022-04-27 10:45:40 -07:00
David Harris	1a8369b02b	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
Ross Thompson	b94927d8a6	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-19 14:09:50 -05:00
Ross Thompson	61dbf13a69	Fixed bug I introduced by csrc cleanup and changes to ILA.	2022-04-17 21:45:46 -05:00
Ross Thompson	3add26be64	fixed no forcing bug in linux testbench.	2022-04-17 17:49:51 -05:00
bbracker	0e183be3e5	fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM	2022-04-14 09:23:21 -07:00
bbracker	489ce4269a	fix ReadDataM forcing	2022-04-13 15:32:00 -07:00
Ross Thompson	65573f07b7	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-13 13:39:47 -05:00
bbracker	016e960401	change interrupt spoofing to happen at negative clock edges	2022-04-13 04:31:23 -07:00
bbracker	3465d8cd32	improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS	2022-04-13 03:37:53 -07:00
bbracker	67ef47b25b	whoops forgot to update AttemptedInstructionCount in interrupt spoofing	2022-04-13 00:49:37 -07:00
bbracker	6c3d274970	change testbench-linux to by default use attempted instruction count for warning/error messages	2022-04-12 21:22:08 -07:00
Ross Thompson	adb4e30c45	Missed the force on uart for no tracking.	2022-04-12 19:37:44 -05:00
Ross Thompson	56bea58a3c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-10 13:41:27 -05:00
Ross Thompson	fc5eac6820	Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.	2022-04-10 13:27:54 -05:00
bbracker	c0c5733a1d	upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs	2022-04-08 13:45:27 -07:00
bbracker	23406d0926	small signs of life on new interrupt spoofing	2022-04-08 12:32:30 -07:00
bbracker	69a0f6e00b	big interrupts refactor	2022-03-30 13:22:41 -07:00
Ross Thompson	e4f4e1bd43	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-30 11:09:44 -05:00
Ross Thompson	997c1b87fe	rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.	2022-03-29 23:48:19 -05:00
Skylar Litz	f91fb7a388	add AtemptedInstructionCount signal	2022-03-26 21:28:57 +00:00
bbracker	6f6663cd67	fix multiple-context PLIC checkpoint generation	2022-03-25 01:02:22 +00:00
bbracker	d33de3ef6b	tabs vs spaces disagreement	2022-03-24 17:11:41 -07:00
bbracker	4b376e2834	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
Ross Thompson	71aad2d213	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
Ross Thompson	aa60b57fb3	Cleanup in testbench-linux.sv.	2022-03-22 22:34:38 -05:00
Ross Thompson	4ca9458534	added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.	2022-03-22 21:28:34 -05:00
Ross Thompson	e6b42cb10f	Added spoof of uart addresses +0x2 and +0x6.	2022-03-22 16:52:27 -05:00
bbracker	742e8d98cd	fix up PLIC and UART checkpointing	2022-03-07 23:48:47 -08:00
bbracker	92e1583db5	change testbench-linux.sv to use new shared location of disassembly files	2022-03-07 20:04:08 -08:00
bbracker	b6031bb15f	fix buildroot checkpointing and add it back to regression	2022-03-02 16:00:19 +00:00
bbracker	a8e8cfb838	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
David Harris	02071700d6	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	5ce8dd60c5	Fixed modelsim warning with linux simulation.	2022-01-31 12:57:02 -06:00
David Harris	090533cfe9	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00