ushakya22
5f916d17d2
Moved order of reading a, b, and result from test vectors file so that result
...
matches up with inputs a and b
2022-02-21 17:28:11 +00:00
ushakya22
3abc2c0592
- created new testbench file instead of having it at the bottom of the srt file
...
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench
Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
2022-02-21 16:24:50 +00:00
ushakya22
1ea3e8120a
- Created exponent divsion module
...
- top module includes exponent module now
Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
2022-02-21 16:13:30 +00:00
ushakya22
3d5b407755
Changed Makefile to compile exptestgen instead of testgen
2022-02-21 16:08:45 +00:00
ushakya22
ec3fa45f86
reverted srt_standford back to original file pre modifications by Udeema
2022-02-21 16:08:09 +00:00
ushakya22
ed452aff5f
verilator lint for srt
2022-02-21 16:05:43 +00:00
ushakya22
a3a572fe5f
Created test vector generation file for exponent and mantissa division
2022-02-21 16:04:41 +00:00
Kip Macsai-Goren
04892c5d38
added scratch register tests for 64 and 32 bits
2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
d852e8a5c1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-21 00:34:54 +00:00
David Harris
4e194b2576
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Kip Macsai-Goren
324efa7d42
added 32 bit pma tests to regression even though they've been working fo a while
2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
dcb5d0f6a9
Added misa test for both 32 and 64 bits
2022-02-18 19:41:50 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
David Harris
3036de316a
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
460b37b21a
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Ross Thompson
beac362364
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
84edb8b5d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
bd7343b791
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
David Harris
131a1a4ded
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
799736632b
Register file comments about reset
2022-02-16 17:21:05 +00:00
Ross Thompson
a64839d999
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
Skylar Litz
03f23d2aaa
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Kip Macsai-Goren
e16581d73d
added CSR permission and minfor to 32 bit tests
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
943c4d9d7c
merged test macros in with 32 bit tests
2022-02-15 20:19:14 +00:00
David Harris
72e83db9fe
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d3034c4f01
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
f734afb866
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
1326ade1a0
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
Kip Macsai-Goren
9ff4025844
light cleanup for privileged tests
2022-02-15 17:06:16 +00:00
Ross Thompson
6076f90bbc
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
David Harris
dee2822359
srt fixes
2022-02-14 18:40:27 +00:00
David Harris
99aacd5aca
srt batch files
2022-02-14 18:37:46 +00:00
ushakya22
f4740cfda4
bring branch back into main
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Merge branch 'srt_division_with_unpacker' into main
2022-02-14 18:25:34 +00:00
ushakya22
4170b54c28
work in progress exponent handling
2022-02-14 18:24:29 +00:00
David Harris
1d5c8a7b98
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
1bb4d46ac1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
e852cb8a31
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec
More cache cleanup.
2022-02-13 12:38:39 -06:00
ushakya22
f87667d120
Added unpacker into testbench for srt
2022-02-12 22:05:18 +00:00
David Harris
b360e7b941
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
a34cbdb7d0
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
