Shreya Sanghai
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4424006624
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added DESIGN_COMPLIER to forgotten config files
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2021-10-12 10:14:04 -07:00 |
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David Harris
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2ae51d1852
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Parameterized number of bits per cycle for integer division
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2021-10-03 01:10:15 -04:00 |
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David Harris
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9ae25b0cea
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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c749d08542
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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David Harris
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e1a1a8395e
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
|
David Harris
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4d40b5faef
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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David Harris
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6bac566bb7
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Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
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2021-07-05 20:35:31 -04:00 |
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David Harris
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80666f0a71
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ross Thompson
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dbd33465e1
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Merge branch 'main' into bigbadbranch
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2021-07-02 11:52:26 -05:00 |
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Ross Thompson
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d6c19e73f4
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Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
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2021-06-25 11:05:17 -05:00 |
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Ross Thompson
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aeeaf6d919
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Progress.
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2021-06-24 13:05:22 -05:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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679e507cc6
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Added SUPPORTED to each peripheral in each config file
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2021-06-17 21:36:32 -04:00 |
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bbracker
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d4aeb1c387
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merge
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2021-06-10 10:03:01 -04:00 |
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bbracker
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0321d74562
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attempt to fix regression by adding PMP_ENTRIES to configs
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2021-06-10 09:59:26 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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Kip Macsai-Goren
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a95a7a7b82
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
|
Merge difficulties
|
2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
|
Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
|
Kip Macsai-Goren
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22e8e06ac7
|
moved privilege dfinitions into wally-constants, upgraded relevant includes
|
2021-06-04 17:55:07 -04:00 |
|
David Harris
|
a26bf37be8
|
Started MMU
|
2021-06-04 11:59:14 -04:00 |
|
Ross Thompson
|
72363f5c66
|
Added the ability to exclude branch predictor.
|
2021-04-26 14:27:42 -05:00 |
|
Ross Thompson
|
8e5409af66
|
Icache integrated!
Merge branch 'icache-almost-working' into main
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2021-04-26 11:48:58 -05:00 |
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Ross Thompson
|
6e803b724e
|
Merge branch 'tests' into icache-almost-working
|
2021-04-25 21:25:36 -05:00 |
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bbracker
|
a3487a9e47
|
do script refactor
|
2021-04-24 09:32:09 -04:00 |
|
Noah Boorstin
|
3f0ead9d4e
|
yay buildroot passes a decent amount of tests now
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
|
2021-04-19 03:26:08 -04:00 |
|
Noah Boorstin
|
6954e6df4c
|
buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
|
2021-04-17 14:44:32 -04:00 |
|
Noah Boorstin
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4f97e9e761
|
start to add buildroot testbench
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
|
2021-04-16 23:27:29 -04:00 |
|
Domenico Ottolia
|
92bb38fa8c
|
Add support for vectored interrupts
|
2021-04-15 19:13:42 -04:00 |
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bbracker
|
31c6b2d01f
|
Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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Ross Thompson
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e1842c8da6
|
Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
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2021-03-23 13:54:59 -05:00 |
|
Noah Boorstin
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77dd0b4504
|
busybear: allow overwriting read values
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2021-03-22 17:28:44 -04:00 |
|
bbracker
|
11d4a8ab34
|
first pass at PLIC interface
|
2021-03-22 10:14:21 -04:00 |
|
Shreya Sanghai
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bbe0957df5
|
Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
|
2021-03-18 17:25:48 -04:00 |
|
Ross Thompson
|
1091dd10c1
|
Switched to gshare from global history.
Fixed a few minor bugs.
|
2021-03-18 16:05:59 -05:00 |
|
Noah Boorstin
|
bc1a0c6ee7
|
change ifndef to generate/if
|
2021-03-18 12:50:19 -04:00 |
|
Noah Boorstin
|
ced2a32d21
|
busybear: update memory map, add GPIO
|
2021-03-18 12:17:35 -04:00 |
|
Noah Boorstin
|
e7fae21eb8
|
busybear: add COUNTERS define
|
2021-03-16 21:08:47 -04:00 |
|
Shreya Sanghai
|
36f0631203
|
added gshare and global history predictor
|
2021-03-16 17:03:01 -04:00 |
|
Shreya Sanghai
|
9eed875886
|
added global history branch predictor
|
2021-03-16 16:06:40 -04:00 |
|
Ross Thompson
|
4c8952de6a
|
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
|
2021-03-15 12:39:44 -05:00 |
|
Noah Boorstin
|
f48af209c4
|
busybear: make CSRs only weird for us
|
2021-03-05 00:46:32 +00:00 |
|
Noah Boorstin
|
26d4024b33
|
busybear: fix bootram range
|
2021-03-01 17:45:21 +00:00 |
|
Noah Boorstin
|
6e70ae8b3d
|
busybear: add 2nd dtim for bootram
|
2021-02-28 16:08:54 +00:00 |
|
Noah Boorstin
|
edd5e9106d
|
busybear: remove gpio, start adding 2nd ram
|
2021-02-28 06:02:40 +00:00 |
|